tag:blogger.com,1999:blog-1228779002887771916.post8712768882400114568..comments2023-11-05T00:21:18.893-07:00Comments on FPGA and DSP from scratch: VHDL Part 26 : Decodertahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.comBlogger2125tag:blogger.com,1999:blog-1228779002887771916.post-23900394419036003682012-04-20T23:33:28.284-07:002012-04-20T23:33:28.284-07:00Hi Rhitee,
yes, i agree. however, so far as this ...Hi Rhitee,<br /><br />yes, i agree. however, so far as this project is concerned, i need to clk the signals otherwise i will have glitches in the output.tahderhttps://www.blogger.com/profile/15461119866495024080noreply@blogger.comtag:blogger.com,1999:blog-1228779002887771916.post-23462087623330328202010-12-20T19:21:20.463-08:002010-12-20T19:21:20.463-08:00heyy decoder is a combinational ciruit.... how r u...heyy decoder is a combinational ciruit.... how r u using clk to generate its output, its independent of it.Reeti Palhttps://www.blogger.com/profile/17886683973053592632noreply@blogger.com