tag:blogger.com,1999:blog-12287790028877719162024-03-05T22:52:30.987-08:00FPGA and DSP from scratchLearning accelerated computing and digital signal processing from the very beginning.tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.comBlogger67125tag:blogger.com,1999:blog-1228779002887771916.post-91638900103080529872008-10-04T08:44:00.000-07:002014-11-18T05:50:40.556-08:00Timing Summary: Maximum output required time after clockThe remaining timing path domain is the <span class="Apple-style-span" style="color: #660000;"><span class="Apple-style-span" style="font-weight: bold;">Maximum output required time after clock</span></span>. According to <a href="http://toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/virtex6.html">Xilinx toolbox</a>, it is the maximum path from inputs to outputs. <a href="http://forums.xilinx.com/xlnx/profile?user.id=138">Gabor</a> from Xilinx forums has a concise explanation on this.<br />
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...<span class="Apple-style-span" style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px; font-family: Arial; font-size: 13px;">"Maximum output required time after clock" refers to the delay from the clock to external outputs of the top-level design for the worst case pins.</span></div>
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Check this <a href="http://forums.xilinx.com/xlnx/board/message?board.id=ISE&message.id=482&query.id=153608">forum</a> for more details.</div>
tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com1tag:blogger.com,1999:blog-1228779002887771916.post-55196058564718822732008-10-04T08:30:00.001-07:002014-01-09T20:22:48.790-08:00Timing Summary: Minimum input arrival time before clockThe second domain in the Timing Summary (Design Summary, Synthesis Report) is the <span class="Apple-style-span" style="color: #660000;"><span class="Apple-style-span" style="font-weight: bold;">Minimum input arrival time before clock</span></span>. Based on <a href="http://toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/virtex6.html">Xilinx toolbox</a>, it is the maximum path from the sequential elements to all primary outputs. Again, <a href="http://forums.xilinx.com/xlnx/profile?user.id=138">Gabor</a> has a very good explanation on this one.<br />
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<span class="Apple-style-span" style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px; font-family: Arial; font-size: 13px;">"Minimum input arrival before clock" is the required setup time from the worst case top-level design input to the clock...</span><span class="Apple-style-span" style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px; font-family: Arial; font-size: 13px;">Again after synthesis these are only estimates, you need to place and route the design to get hard numbers. Also if your design as synthesized represents only a portion of a larger design, the input and output timings may be significantly different, as they may not represent signals going on or off of the FPGA.</span></div>
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He also stressed that if the time indicated in "Minimum input arrival before clock" is less than the time in the "Minimum Period", it may be possible to run the design at the maximum clock frequency specified.</div>
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Click here to get to the <a href="http://forums.xilinx.com/xlnx/board/message?board.id=ISE&message.id=482&query.id=153608">source</a>.</div>
tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-55495688056899069912008-10-04T08:11:00.000-07:002014-01-09T20:23:23.588-08:00Timing Summary: Minimum PeriodThe first item in the list is the Minimum period, one of the domains of timing paths. According to <a href="http://toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/virtex6.html">Xilinx toolbox</a>, it is the maximum path from all primary inputs to the sequential elements. One good explanation is given by, again, <a href="http://forums.xilinx.com/xlnx/profile?user.id=138">gszakacs</a> in a Xilinx forum.<br />
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<span class="Apple-style-span" style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px; font-family: Arial; font-size: 13px;">Minimum period" after synthesis is an estimate of the clock period for signals inside the design. Thus you can invert this to get a feel for maximum clock frequency. This is not a hard actual number, as you can only see the true numbers after place&route. Also this may not be the actual minimum period for the design if you are limited by input and output timing. It only calculates the worst case path timing from clock edge to clock edge for flip-flops within the design. So if you have a path consisting of external input to flip-flop through look-up table to another flip-flop to an external output, only the path from the first flip-flop through the look-up table to the second flip-flop is measured for "Minimum period".</span></div>
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<span class="Apple-style-span" style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px; font-family: Arial; font-size: 13px;">The minimum clock period depends on paths that go from the Q output of a flip-flip to the D input of another flip-flop in the design...</span><span class="Apple-style-span" style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px; font-family: Arial; font-size: 13px;">The worst case path may in fact not be connected at the top level. You would need to look at a static timing report to see what the path is and whether you use it...</span><span class="Apple-style-span" style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px; font-family: Arial; font-size: 13px;">Also note that the timing reported by synthesis is a best-guess estimate of the achievable timing after place and route. This is usually only useful when designing reusable IP for example or some other subsystem you would like to know the possible best case speed of. The real timing performance of a design is only known after place & route and can be found in the post P&R static timing report. Using the advanced properties for static timing report generation you can get a verbose report that includes uncovered paths in case there are critical paths that have not been constrained.</span></div>
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You may want to visit that <a href="http://forums.xilinx.com/xlnx/board/message?board.id=ISE&message.id=482&query.id=153608">forum</a>.</div>
tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-84243585259023096992008-10-04T04:12:00.000-07:002014-01-09T20:23:41.845-08:00Maximum combinational path delay: No path foundIn the Design Summary, under Synthesis Report (Timing Summary heading), I always see this list:<br />
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The last item interests me most (among the four) since it sometimes gives me this: </div>
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<span class="Apple-style-span" style="font-weight: bold;"><span class="Apple-style-span" style="color: #660000;">Maximum combinational path delay: No path found.</span></span></div>
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I do not know whether this is good. So I checked. In a Xilinx <a href="http://forums.xilinx.com/xlnx/board/message?board.id=ISE&message.id=482&query.id=153608">forum</a>, expert contributor <a href="http://forums.xilinx.com/xlnx/profile?user.id=138">gszakacks </a>said,</div>
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<span class="Apple-style-span" style="font-style: italic;">This is normal if there is no path from a top-level input to a top-level output that is not clocked. I assume your design is <span class="Apple-style-span" style="font-weight: bold;">fully pipelined</span>, thus no combinatorial paths from input to output?</span></div>
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According to a Xilinx ModelSim Simulation <a href="http://www.cis.upenn.edu/~milom/cse372-Spring06/simulation/">Tutorial</a> from <a href="http://www.cis.upenn.edu/">Computer and Information Science, University of Pennsylvania</a>, </div>
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<span class="Apple-style-span" style="font-style: italic;">Maximum combinational path delay...is the maximum delay for signal propagation in your design, so changing signals faster than [this] will result in unexpected behavior.</span></div>
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They have an example <a href="http://www.cis.upenn.edu/~milom/cse372-Spring06/simulation/">there</a> (Timing Simulation: Combinational Logic Section 2), where they made the signal transition faster which resulted in simulation failure - the output signals do not match the input signals because the inputs change too fast.</div>
tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com1tag:blogger.com,1999:blog-1228779002887771916.post-59934145719235314742008-10-04T03:11:00.000-07:002008-10-04T04:10:37.379-07:00Critical PathI heard of 'critical path' for the first time yesterday during a meeting. Our project leader was asking about an incorrect output in the main block. My teammate explained about a part in his design that is asynchronous. Then the proj leader mentioned 'critical path'. I do not know what it is so I did some reading. According to <a href="http://www.amazon.com/Design-Recipes-FPGAs-Peter-Wilson/dp/0750668458/ref=pd_bbs_sr_1?ie=UTF8&s=books&qid=1223116039&sr=8-1">Design Recipes for FPGAs</a>, during analysis of static timing, the delay from each input to each output of all devices is computed. The delays are then added up along each path through the circuit to get the critical path through the design. The fastest design speed is therefore obtained. The critical path is an approach to logic optimization.<div><br /></div><div><div><div>Reference:<br /></div><div>(1) Wilson, P., Design Recipes for FPGAs, 2007, pp. 40 and187, Elsevier.</div></div></div>tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-27704151027989566842008-09-29T17:12:00.001-07:002008-10-02T23:37:19.950-07:00Writing techware documentation<div>I feel so terribly burdened by having to do documentation. I had already spent 4 days with it (still counting) and I'm so slow in doing it. I know this is important in reconfigurable computing advocacy but my problem is, I'm not so good with words. I especially hate highfalutin techie words that only geeks will understand but not the common people. There. That's my problem. How do I relay such a beautiful thing as accelerated computing to young people without them being terrified that this is something they might not be able to grasp? I don't know how to start with this so I need at least a reference. I want a book that will give me just what I need. I don't want to spend too much time in writing. I want to practice coding. So I checked <a href="http://www.amazon.com/">amazon</a> for a guide to writing with good reviews. I saw "<a href="http://www.amazon.com/Writing-Computer-Science-Justin-Zobel/dp/1852338024/ref=pd_bbs_sr_1?ie=UTF8&s=books&qid=1222734688&sr=1-1">Writing for Computer Science</a>" by Justin Zobel has excellent reviews (5 reviews only :)).<br /></div><div><br /></div><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjhn1CsW9xR5q-Rtoodgy4-CSJd7DzBID829ogi5KUyJOIb278STjuNhOEFmHwGLdi2-U7CWMy-GJjTFzwQvQdW5Md24do71qFyFZo6nPn3IgY21Kn36fvGuzJf2jRPqvUEoPwo2uzH41c/s1600-h/wrt.JPG"><img style="display:block; margin:0px auto 10px; text-align:center;cursor:pointer; cursor:hand;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjhn1CsW9xR5q-Rtoodgy4-CSJd7DzBID829ogi5KUyJOIb278STjuNhOEFmHwGLdi2-U7CWMy-GJjTFzwQvQdW5Md24do71qFyFZo6nPn3IgY21Kn36fvGuzJf2jRPqvUEoPwo2uzH41c/s320/wrt.JPG" border="0" alt="" id="BLOGGER_PHOTO_ID_5251608962569577682" /></a><br />I'm excited to quickly read this one since it only has less than 200 pages. There's a relatively high probability I'll be able to finish this tomorrow. Hope this could speed me up and help me finish writing within this week.<div><br /></div><div><span class="Apple-style-span" style="font-weight: bold;">Addendum (Oct. 03, 2008): </span></div><div>The book is very good! I just have to finish documenting one block. Hopefully, I'll be able to go back to coding this weekend!</div>tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com1tag:blogger.com,1999:blog-1228779002887771916.post-12497506516751532532008-09-24T22:22:00.000-07:002008-09-24T22:58:42.192-07:00VHDL Code for UART (transmitter only)I used UART to check my outputs bit-by-bit for the previous project that I did. Unfortunately, since I needed only a transmitter, the VHDL code that I have is only for the TX. I would like to settle first the answer to my question, "What is UART?" I found a very clear and simple discussion from the site of <a href="http://www.blogger.com/www.rose-hulman.edu/~simoni/Classes/EC551/ProjectInfo/UARTChallenge.pdf">Rose-Hulman Institute of Technology</a>. UART stands for <span class="Apple-style-span" style="font-weight: bold;">Universal Asynchronous Receiver Transmitter</span>. It is a parallel to serial data transmitter and a serial to parallel data receiver. The 'Asynchronous' term is there because of the fact that the clock for the UART need not be synchronized to either transmit or receive system clocks. I needed this UART to send my data outputs to my CPU's buffer and have <a href="http://www.mathworks.com/">MATLAB</a><span class="Apple-style-span" style=" ;font-family:'Times New Roman';">®</span> check those bits. My input ports are clock, reset, my input data (from 1 to n depending on the number of outputs that I need to read, remember number of outputs not the number of bits) and of course, my output which is just a <span class="Apple-style-span" style="color: rgb(204, 51, 204);">std_logic</span> type. The simple technique my teammate taught me is to use a counter that is triggered by a synchronous enable. For example, I need to read 4 outputs from my main block. This 4 bit vectors will be fed to the input of my UART. Those 4-bit vectors are, say, 8 bits each. The first count of the counter (my UART) will be for the start bit, the next 8 contains the data, the last bit, the tenth bit will be the stop bit. The start and stop bits are necessary for every UART. This repeats for all my data. For every count, these bits will be fed to the 1-bit output. I show below a sample portion, taken from the middle of my code.<div><br /></div><div><div><span class="Apple-style-span" style="color: rgb(51, 102, 255);">when </span>111=>output<='0';<span class="Apple-style-span" style="color: rgb(51, 204, 0);">--this is the start bit</span></div><div><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">when </span>112=> output <=input10(0);</div><div><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">when </span>113=> output <=input10(1);</div><div><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">when </span>114=> output <=input10(2);</div><div><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">when </span>115=> output <=input10(3);</div><div><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">when </span>116=> output <=input10(4);</div><div><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">when </span>117=> output <=input10(5);</div><div><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">when </span>118=> output <=input10(6);</div><div><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">when </span>119=> output <=input10(7);</div><div><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">when </span>120=> output <='1';<span class="Apple-style-span" style="color: rgb(51, 204, 0);">--this is the stop bit</span></div><div><span class="Apple-style-span" style="color: rgb(51, 204, 0);"><br /></span></div><div>For instance, my count ended at 120. After closing my case statement I added an if-end if statement that just says if the counter is less than 200 then increment the counter. I was adviced to have larger number for my counter. Notice that I used 200 instead of 120 as my upper limit. </div></div>tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-63806757133434034382008-09-22T18:15:00.000-07:002008-09-28T21:10:10.124-07:00Best FPGA introductory book<a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhnxzOrMHCUXkbilyr51jAz4k1Xr8YjMusu4BPdrJsoi7X19HyMt5OmD11mJmTOTlQy4V5-wfk5xI0pSAIiHb5s8feF8B0PWAan0xZCB0n2CFE7r47lF0ehuPww0KtjwwEXWfxRTqsFDQA/s1600-h/Chu.jpg"><img style="display:block; margin:0px auto 10px; text-align:center;cursor:pointer; cursor:hand;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhnxzOrMHCUXkbilyr51jAz4k1Xr8YjMusu4BPdrJsoi7X19HyMt5OmD11mJmTOTlQy4V5-wfk5xI0pSAIiHb5s8feF8B0PWAan0xZCB0n2CFE7r47lF0ehuPww0KtjwwEXWfxRTqsFDQA/s200/Chu.jpg" border="0" alt="" id="BLOGGER_PHOTO_ID_5249020345879148946" /></a><br />Like all FPGA starters, I also struggled for a book that will serve as an FPGA tutorial. It was only this year (copyright of this book is February 2008) that I found one. This is for me (so far) the best introductory FPGA book--<a href="http://www.amazon.com/FPGA-Prototyping-VHDL-Examples-Spartan-3/dp/0470185317/ref=sr_1_1?ie=UTF8&s=books&qid=1222132391&sr=8-1">FPGA Prototyping by VHDL Examples</a>, authored by Pong Chu. Learning by doing is the most effective pedagogical style and this book did not fail to deliver that one. I find Pong Chu's writing style very easy to understand because the discussions are clear. That is the most essential thing in relaying knowledge to a beginner -- clarity. That's enough for me. I don't need to say more about it.tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com1tag:blogger.com,1999:blog-1228779002887771916.post-43630860798143344982008-09-21T16:45:00.000-07:002008-09-21T17:04:16.125-07:00An FPGA ApplicationI think one of the more promising applications of FPGA is in real-time visualization. To be able to have a solid foundation on this, I need to study graphics first or say, Digital Image Processing. I am currently reading a documentation of the Master's thesis (March 2005) entitled An FPGA-based 3D Graphics System by <span class="Apple-style-span" style="font-weight: bold;">Niklas Knutsson</span> of <a href="http://www.blogger.com/www.lith.liu.se/en/">Link</a><span class="Apple-style-span" style=" ;font-family:'Times New Roman';"><a href="http://www.blogger.com/www.lith.liu.se/en/">ö</a><span class="Apple-style-span" style=" ;font-family:Georgia;"><a href="http://www.blogger.com/www.lith.liu.se/en/">ping Institute of Technology</a>. His abstract goes like this.</span></span><div><br /></div><div><div><span class="Apple-style-span" style="font-style: italic;">This report documents the work done by the author to design and implement a 3D graphic system on an FPGA (Field Programmable Gate Array). After a preamble with a background presentation to the project, a very brief introduction in computer graphics techniques and computer graphics theory is given. Then, the hardware available to the project, along with an analysis of general requirements is examined. The following chapter contains the proposed graphics system design for FPGA implementation. A broad approach to separate the design and the eventual implementation was used. Two 3D pipelines are suggested - one fully capable high-end version and one which use minimal resources. The documentation of the effort to implement the minimal graphics system previously discussed then follows. The documentation outlines the work done without going too deep into detail, and is followed by the largest of the tests conducted. Finally, chapter seven concludes the project with the most important project conclusions and some suggestions for future work. </span></div><div><br /></div><div><br /></div><div>I am after knowing the framework of such an application since there are already lots of books that discuss the physics of real-time graphics. I find quite few papers, much less books, that discusses the implementation of image processing on FPGA.</div><div><br /></div></div>tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-82945241376054282612008-09-20T06:28:00.000-07:002008-09-20T08:33:15.269-07:00VHDL Part 51 : Debouncer<div>I find debouncing circuits very handy. Not only when I checked the test vector outputs of my design, but whenever I need to use a signal's event to trigger another signal. Debouncing solves the problem I encountered whenever I use the mechanical switches in the FPGA board particularly the push buttons. Mechanical switch bounces that when I push it once, the output could be three times the supposed signal. Good thing, I tried the <a href="http://www.xilinx.com/">Xilinx ISE 9.2i</a> in-depth guide before, I learned that ISE has a template for a debouncer. Templates are accessed by the icon below.</div><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiOCGKmDjDtBxiECPTWENW2qrBQgVRxAmzFfFp7HqvtoXtfXeJ9-CXsEqPecqB_2byR8w2fd30ZRw2LhY7Ay0thj7yo0TMaZ2Vt_EfbeR1NrV_B52mNRj5Kmgz4n4tvJ6cgShWRIf6llXs/s1600-h/temp.JPG" style="text-decoration: none;"><img style="text-decoration: underline;display: block; margin-top: 0px; margin-right: auto; margin-bottom: 10px; margin-left: auto; text-align: center; cursor: pointer; " src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiOCGKmDjDtBxiECPTWENW2qrBQgVRxAmzFfFp7HqvtoXtfXeJ9-CXsEqPecqB_2byR8w2fd30ZRw2LhY7Ay0thj7yo0TMaZ2Vt_EfbeR1NrV_B52mNRj5Kmgz4n4tvJ6cgShWRIf6llXs/s400/temp.JPG" border="0" alt="" id="BLOGGER_PHOTO_ID_5248103269228384850" /></a><div>On the tree at the left of the Language Templates subwindow, expand VHDL, then Synthesis Constructs > Coding Examples > Misc > Debounce Circuits. I played with the code trying to put the statement for the output within the clock statement. I also inverted the signals used to solve the output. Debouncers have been very useful to me.<br /></div>tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-41954241447094448752008-09-20T02:02:00.000-07:002008-09-20T02:40:04.587-07:00VHDL Part 50 : Accessing the Serial PortI was such in a hurry that time when I had just finished porting the search algorithm I was working on to VHDL. It ran in the FPGA board but the results I see are on the LEDs. I cannot check the output with the LEDs since they are fast even if I had set the clock so slow for me to see the transitions I still cannot read with it. To be sure, I was adviced by my teammate to read the serial port using <a href="http://www.mathworks.com/">Matlab</a><span lang="EN-GB" style="font-size:12.0pt;mso-bidi-font-family:"Times New Roman";mso-fareast-Times New Roman"; mso-ansi-language:EN-GB;mso-fareast-language:EN-US;mso-bidi-language:AR-SAfont-family:";font-size:10.0pt;"><a href="http://www.mathworks.com/">®</a></span>. My inputs will be generated by a counter that with each count, it will give the necessary inputs to my main block. To do that I first need a UART transmitter and use the push-down button on the FPGA board as my clock. In using the push-down button as the clock, I need to add a debouncing circuit to control it because one push could give several clocks. This is what I did to access the serial port on the FPGA board I am using.tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-90658235669153924192008-09-18T15:56:00.000-07:002008-09-18T16:50:08.055-07:00VHDL Part 49 : Re Mask Generator, Third SolutionApparently, I am not the only one that has this problem. I had found a way to solve the mask generator problem by looking in forums such as the one posted in VelocityReviews titled <a href="http://www.velocityreviews.com/forums/t23818-generic-shift-register-where-value-n-keeps-changing.html">VHDL - generic shift register where value 'n' keeps changing</a>. Though our circuits are different, we both struggled with mapping the generics based on an input signal. The generics have to be compiled during runtime that's why I have errors as posted on the previous post (<a href="http://fpga-dsp-scratch.blogspot.com/2008/09/vhdl-part-48-mask-generator-third.html">VHDL Part 48</a>). What Ralph Hildebrandt suggested in that post was to model a shift register (whatever component it is) wide enough for the worst case. He also noted that all the time, those flipflops is included. It was sound enough. That is what I followed. Whatever component I/O ports you put in the FPGA board has to be fixed for obvious reasons.tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-80094534680786485982008-09-16T19:39:00.000-07:002008-09-16T19:51:07.240-07:00VHDL Part 48 : Mask Generator, Third SolutionI cannot use the second solution. The problem with it is that the inputs have to be fixed. The mask generator that we want to do has to be flexible where the components' ports and signals depend on the length of the input. My teammate will give me an input for the valid length then I plan to convert it to integer and use it as a parameter with which I will map my subblock generics. The problem is this method produced errors all have to do with the following:<div><br /></div><div style="text-align: center;"><span class="Apple-style-span" style="font-family: arial; font-size: 13px; ">The actual value [<span class="Apple-style-span" style="font-style: italic;">signal_name</span>] associated with a generic must be a globally static expression.</span><br /></div><div><br /></div><div>I have to look for another way.</div>tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-22604225547105889962008-09-16T00:06:00.000-07:002008-09-16T00:16:05.988-07:00'reconfiguration' in FPGAMy teammate and I are problematic (I know he is; he doesn't know I am) about the fact that VHDL does not support reconfiguration right now. Don't get me wrong. The technology is reconfigurable by the fact that it is an FPGA board. The abstract of our project says that what's good here is the 'reconfigurability' of the board we are using when you can't actually reconfigure the board during runtime. The bright side here, as I see it, is that this is another room for study. Maybe what will happen with us is that we will implement applications and tackle the problem as we encounter it. I haven't got much time to study it all. Seems like my next two years is already programmed. I'll burn the bridge when I get there.tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-57465227039495973382008-09-15T20:41:00.000-07:002008-09-15T20:42:32.484-07:00VHDL Part 47: Mask Generator, Second Solution<p style="margin-bottom: 0in">I was thinking for another solution after those posts. My project leader suggested a design that I gladly worked on. It is done by cascading an encoder, a decoder, and a register. Then having several instances of this network depending on the pattern that I want to have. My outputs are obtained from the registers. The final output is obtained by having a selector decide which output index must be taken. I'm sorry I cannot post the code here. Intellectual property man..which I am very much against.</p>tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-5780353731383689882008-09-14T19:02:00.000-07:002008-09-14T19:07:35.203-07:00VHDL Part 46 : Mask Generator 5And so I said:<div><br /></div><div><span class="Apple-style-span" style=" ;font-family:arial;font-size:13px;">jeppe,</span><br /></div><div><span class="Apple-style-span" style=" ;font-family:arial;font-size:13px;"><br />1. I hadn't tried it yet in other languages.<br />2. I have been using paper and pen too for this thinking I might find some other way to manipulate the flow.<br />3. I am just considering 3 for n and 5 for r.</span><br /></div><div><span class="Apple-style-span" style=" ;font-family:arial;font-size:13px;"><br /></span></div><div><span class="Apple-style-span" style=" ;font-family:arial;font-size:13px;"><span class="Apple-style-span" style=" ;font-family:Georgia;font-size:16px;">I did not pursue using arrays anymore for this mask gen. (Though I was glad to be able to try vhdl arrays). The fact that I will be inferring a large amount of combinatorial circuits made me decide to switch to other possible designs. This conversation took place March this year.</span><br /></span></div>tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-31919412117316639672008-09-14T19:00:00.000-07:002008-09-14T19:01:34.718-07:00VHDL Part 45 : Mask Generator 4To which he patiently replied:<div><br /></div><div><span class="Apple-style-span" style="font-family: arial; font-size: 13px; ">My "fast" answer without getting into details.<br />1) Have you tried this algoritme in other languages like C or Java.<br />2) Have you draw the data structures at a paper checking the flow. <br />3) A got a feeling your about to create a huge combinatorial network which in the end will take up to much space.<br />May be should you consider a "pipelined" design in which you works at parts of the arrays. This will however cost you time instead of logic.<br /><br />Jeppe</span><br /></div>tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-37024802758388191632008-09-14T18:56:00.000-07:002008-09-14T18:59:56.685-07:00VHDL Part 44 : Mask Generator 3I tried his code and added some lines so that I could tap a row for the output. However, I could not view the RTL schematic so I posted a follow up question.<div><br /></div><div><span class="Apple-style-span" style=" ;font-family:arial;font-size:13px;">Hi jeppe<br /><br />Thank you so much for helping me. <br /><br /><br />I had added some lines of code so that I could access a row for the output.<br /><br /><span style="color:Blue;">for j in 0 to r-1 loop<br />for i in 0 to n-1 loop<br />if maskIn_P(i) = maskIn_R(j) then<br />memory(i)(j) <= '1'; <i>--THIS IS LINE 68</i><br />else<br />memory(i)(j) <= '0'; end if; end loop; end loop; elsif readEn = '1' then maskOut <= memory(conv_integer(address)); else maskOut <= "ZZZZZ"; end if; end if; end process; </span><br /><br />Here's my port declaration:<br /><br /><span style="color:Blue;">address : in STD_LOGIC_VECTOR (r-1 downto 0);<br />patternIn : in STD_LOGIC_VECTOR (n-1 downto 0);<br />referenceIn : in STD_LOGIC_VECTOR (r-1 downto 0);<br />maskOut : out STD_LOGIC_VECTOR (n-1 downto 0));</span><br /><br /><br />I got no error in checking the syntax but got one when I tried to view the RTL schematic. <br /><span style="color:Blue;">line 68: Index value <8> is not in Range of array <memory><0>>.<br /></memory></span><br />I'm not sure but I have a feeling that the error is caused by this line<br /><span style="color:Blue;">maskOut <= memory(conv_integer(address));</span><br /><br />Is it necessary for n and r to be equal? I had tried letting n be equal to 8 and r to 32<br />but it won't synthesize. When I tried using your values which is 10 for both, it did <br />synthesize. So long as n and r are equal it synthesized. But I can't have have equal values for n and r <br />since my reference vector must be much longer than my pattern vector.<br /><br />Thanks again,<br />tahder</span><br /></div>tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-41811168157875440932008-09-14T18:52:00.000-07:002008-09-14T18:55:23.468-07:00VHDL Part 43 : Mask Generator 2<a href="http://www.jjmk.dk">Jeppe</a> is kind enough to answer me. Here it goes.<div><br /></div><div><span class="Apple-style-span" style="font-family: arial; font-size: 13px; ">Hi tahder<br /><br />Not sure - but I guess the generate statement not allowed inside a process.<br /><br />try this instead<br /></span></div><div><span class="Apple-style-span" style="font-family: arial; font-size: 13px;"><br /></span></div><div><span class="Apple-style-span" style="font-family: arial; font-size: 13px;"><span class="Apple-style-span" style="font-family: -webkit-monospace; white-space: nowrap; "><span style="color: rgb(0, 119, 0); ">---------------------------------------------------------------------------------- <br /></span><span style="color: rgb(0, 0, 187); ">library IEEE</span><span style="color: rgb(0, 119, 0); ">; <br />use </span><span style="color: rgb(0, 0, 187); ">IEEE</span><span style="color: rgb(0, 119, 0); ">.</span><span style="color: rgb(0, 0, 187); ">STD_LOGIC_1164</span><span style="color: rgb(0, 119, 0); ">.</span><span style="color: rgb(0, 0, 187); ">ALL</span><span style="color: rgb(0, 119, 0); ">; <br />use </span><span style="color: rgb(0, 0, 187); ">IEEE</span><span style="color: rgb(0, 119, 0); ">.</span><span style="color: rgb(0, 0, 187); ">STD_LOGIC_ARITH</span><span style="color: rgb(0, 119, 0); ">.</span><span style="color: rgb(0, 0, 187); ">ALL</span><span style="color: rgb(0, 119, 0); ">; <br />use </span><span style="color: rgb(0, 0, 187); ">IEEE</span><span style="color: rgb(0, 119, 0); ">.</span><span style="color: rgb(0, 0, 187); ">STD_LOGIC_UNSIGNED</span><span style="color: rgb(0, 119, 0); ">.</span><span style="color: rgb(0, 0, 187); ">ALL</span><span style="color: rgb(0, 119, 0); ">; <br /><br /></span><span style="color: rgb(0, 0, 187); ">entity mskgen is <br /> generic</span><span style="color: rgb(0, 119, 0); ">( </span><span style="color: rgb(0, 0, 187); ">n</span><span style="color: rgb(0, 119, 0); ">: </span><span style="color: rgb(0, 0, 187); ">natural </span><span style="color: rgb(0, 119, 0); ">:= </span><span style="color: rgb(0, 0, 187); ">10</span><span style="color: rgb(0, 119, 0); ">; <br /> </span><span style="color: rgb(0, 0, 187); ">r</span><span style="color: rgb(0, 119, 0); ">: </span><span style="color: rgb(0, 0, 187); ">natural </span><span style="color: rgb(0, 119, 0); ">:= </span><span style="color: rgb(0, 0, 187); ">10</span><span style="color: rgb(0, 119, 0); ">); <br /> </span><span style="color: rgb(0, 0, 187); ">port</span><span style="color: rgb(0, 119, 0); ">( </span><span style="color: rgb(0, 0, 187); ">clk</span><span style="color: rgb(0, 119, 0); ">,</span><span style="color: rgb(0, 0, 187); ">maskEn</span><span style="color: rgb(0, 119, 0); ">: </span><span style="color: rgb(0, 0, 187); ">std_logic</span><span style="color: rgb(0, 119, 0); ">); <br /></span><span style="color: rgb(0, 0, 187); ">end mskgen</span><span style="color: rgb(0, 119, 0); ">; <br /><br /></span><span style="color: rgb(0, 0, 187); ">architecture bhv of mskGen is <br /> subtype patternArray is std_logic_vector </span><span style="color: rgb(0, 119, 0); ">(</span><span style="color: rgb(0, 0, 187); ">n</span><span style="color: rgb(0, 119, 0); ">-</span><span style="color: rgb(0, 0, 187); ">1 downto 0</span><span style="color: rgb(0, 119, 0); ">); <br /> </span><span style="color: rgb(0, 0, 187); ">type referenceArray is </span><span style="color: rgb(0, 119, 0); ">array (</span><span style="color: rgb(0, 0, 187); ">r</span><span style="color: rgb(0, 119, 0); ">-</span><span style="color: rgb(0, 0, 187); ">1 downto 0</span><span style="color: rgb(0, 119, 0); ">) </span><span style="color: rgb(0, 0, 187); ">of patternArray</span><span style="color: rgb(0, 119, 0); ">; <br /> </span><span style="color: rgb(0, 0, 187); ">signal memory</span><span style="color: rgb(0, 119, 0); ">,</span><span style="color: rgb(0, 0, 187); ">maskIn_P</span><span style="color: rgb(0, 119, 0); ">,</span><span style="color: rgb(0, 0, 187); ">maskIn_R </span><span style="color: rgb(0, 119, 0); ">: </span><span style="color: rgb(0, 0, 187); ">referenceArray</span><span style="color: rgb(0, 119, 0); ">; <br /><br /></span><span style="color: rgb(0, 0, 187); ">begin <br /> process </span><span style="color: rgb(0, 119, 0); ">(</span><span style="color: rgb(0, 0, 187); ">clk</span><span style="color: rgb(0, 119, 0); ">, </span><span style="color: rgb(0, 0, 187); ">maskEn</span><span style="color: rgb(0, 119, 0); ">) <br /> </span><span style="color: rgb(0, 0, 187); ">begin <br /> </span><span style="color: rgb(0, 119, 0); ">if </span><span style="color: rgb(0, 0, 187); ">clk </span><span style="color: rgb(0, 119, 0); ">= </span><span style="color: rgb(221, 0, 0); ">'1' </span><span style="color: rgb(0, 119, 0); ">and </span><span style="color: rgb(0, 0, 187); ">clk</span><span style="color: rgb(221, 0, 0); ">'event then <br /> if maskEn = '</span><span style="color: rgb(0, 0, 187); ">1</span><span style="color: rgb(221, 0, 0); ">' then <br /> for j in 0 to r-1 loop <br /> for i in 0 to n-1 loop <br /> if maskIn_P(i)=maskIn_R(j) then <br /> memory(i)(j) <= '</span><span style="color: rgb(0, 0, 187); ">1</span><span style="color: rgb(221, 0, 0); ">'; <br /> else <br /> memory(i)(j) <= '</span><span style="color: rgb(0, 0, 187); ">0</span><span style="color: rgb(0, 119, 0); ">; <br /> </span><span style="color: rgb(0, 0, 187); ">end </span><span style="color: rgb(0, 119, 0); ">if; <br /> </span><span style="color: rgb(0, 0, 187); ">end loop</span><span style="color: rgb(0, 119, 0); ">; <br /> </span><span style="color: rgb(0, 0, 187); ">end loop</span><span style="color: rgb(0, 119, 0); ">; <br /> </span><span style="color: rgb(0, 0, 187); ">end </span><span style="color: rgb(0, 119, 0); ">if; <br /> </span><span style="color: rgb(0, 0, 187); ">end </span><span style="color: rgb(0, 119, 0); ">if; <br /> </span><span style="color: rgb(0, 0, 187); ">end process</span><span style="color: rgb(0, 119, 0); ">; <br /></span><span style="color: rgb(0, 0, 187); ">end bhv</span><span style="color: rgb(0, 119, 0); ">; </span></span><br /></span></div><div><span class="Apple-style-span" style="color: rgb(0, 119, 0); font-family: -webkit-monospace; font-size: 13px; white-space: nowrap;"><br /></span></div><div><span class="Apple-style-span" style="color: rgb(0, 119, 0); font-family: -webkit-monospace; font-size: 13px; white-space: nowrap;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: arial; white-space: normal; ">Regards<br />Jeppe</span><br /></span></div>tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-54162540616686984522008-09-14T18:48:00.000-07:002008-09-14T19:36:09.397-07:00VHDLPart 42 : Mask Generator 1Let me share the conversation that I had with <a href="http://www.jjmk.dk/">jeppe</a> from the vhdl forum in <a href="http://www.velocityreviews.com/">VelocityReviews</a>. This is the question I posted (taht was March 2008).<div><br /></div><div><span class="Apple-style-span" style=" ;font-family:arial;font-size:13px;">Hello everyone,<br />I am new to vhdl and I want to implement a synthesizable mask generator. <br />I thought about implementing it with a 2D array (like a ROM) that is usually seen in vhdl books.<br />My problem is that I'm stuck with generating the contents inside the array since an index will output a '1' only if an n-bit element is equal to another n-bit element. I don't want to have a build up of equality comparators. Is it possible to have only one comparator for the whole system? or a single row of comparators that will work for all the rows in the memory? I tried doing this:<br /><br />architecture bhv of maskGen is<br /><br />subtype patternArray is std_logic_vector (n-1 downto 0);<br />type referenceArray is array (r-1 downto 0) of patternArray;<br />signal memory : referenceArray;<br /><br />-- this is for the magnitude comparator<br />component magComp<br />port (A, B : in std_logic_vector (n-1 downto 0);<br />EQ : out std_logic);<br />end component;<br /><br />-- The behavioral architecture for magComp is only:<br />-- EQ <= '1' when A=B else '0'; begin process (rst, clk, maskEn) begin if clk = '1' and clk'event then if maskEn = '1' then for j in 0 to r-1 loop for i in 0 to n-1 generate -- this is line 69 magComp port map (A=>maskIn_P(i), B=>maskIn_R(j), EQ => memory(i)(j));<br />end generate;<br />end loop;<br />end if;<br />end if;<br /><br />end process;<br />end bhv;<br /><br /><br />However, this gave me an error:<br />Line 69. parse error, unexpected GENERATE, expecting LOOP.<br /><br />Can anyone explain why the code generated such an error? <br /><br />I really do not want to implement the code above since it might result to horrendous amount of logic.<br />What do I do now? <br /><br />Thanks,<br />tahder</span><br /></div>tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-11773721351704694042008-09-14T15:51:00.000-07:002008-09-14T23:09:29.168-07:00VHDL Part 41 : ArraysI happen to take interest in vhdl arrays when I was trying to come up with a code for mask generator. A mask generator is like a multplication table where you have values along x and along y and to get a '1', certain values for x and y must be satisfied. I was trying to come up with a design that won't build a tremendous amount of logic so I tried to check out arrays.<div><br /><div>Arrays in VHDL can be 1D, 2D or 1Dx1D.</div><div><br /></div><div>Here is a scalar : 0</div><div>Here is a 1D : </div><div>11001</div><div>Here is a 1Dx1D :</div><div>11001</div><div>10100</div><div>00101</div><div>11100</div><div>Here is a 2D :</div><div>1 1 0 0 1</div><div>1 0 1 0 0</div><div>0 0 1 0 1</div><div>1 1 1 0 0</div><div><br /></div><div>I just have a problem with these. According to the book <span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px; font-size:13px;"><a href="http://www.amazon.com/Circuit-Design-VHDL-Volnei-Pedroni/dp/0262162245/ref=pd_bbs_sr_1?ie=UTF8&s=books&qid=1219546493&sr=8-1" style="color: rgb(119, 102, 68); text-decoration: none; ">Circuit Design with VHDL</a>, they are<span class="Apple-style-span" style="font-weight: bold;"> generally not synthesizable</span>.</span> </div><div><br /></div><div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px; font-size:13px;">Reference:</span><br /></div><div><span class="Apple-style-span" style="line-height: 20px; "><span class="Apple-style-span" style="color: rgb(51, 51, 51); font-size:13px;">(1) Pedroni, V., <a href="http://www.amazon.com/Circuit-Design-VHDL-Volnei-Pedroni/dp/0262162245/ref=pd_bbs_sr_1?ie=UTF8&s=books&qid=1219546493&sr=8-1" style="color: rgb(119, 102, 68); text-decoration: none; ">Circuit Design with VHDL</a>, The MIT Press, 2004.</span></span></div></div><div><br /></div></div>tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-2707074931060035832008-09-13T22:43:00.000-07:002008-09-14T00:37:19.808-07:00VHDL Part 40 : Declaring Components in PackagesIf I use a code as a component, I can then use it in another circuit which allows me to create designs in hierarchy. I find this good since it enables code reusability. However, I find it tiring to declare codes/components again and again everytime I revise my topblock. I sometimes place these components in a library so that I can do away with explicitly writing such codes.<div><br /></div><div>For instance I need to instantiate a shift register, 4-bit register, a decoder and an encoder. So first I have to create individual codes for each of these 4 circuits. You may see my previous posts for their sample codes. </div><div><br /></div><div>4-bit register -- <a href="http://fpga-dsp-scratch.blogspot.com/2008/08/vhdl-part-5-n-bit-register.html">VHDL Part 5</a></div><div>shift register -- <a href="http://fpga-dsp-scratch.blogspot.com/2008/08/vhdl-part-10-n-bit-shift-rightshift.html">VHDL Part 10</a></div><div>encoder -- <a href="http://fpga-dsp-scratch.blogspot.com/2008/08/vhdl-part-29-priority-encoder.html">VHDL Part 29</a><br /></div><div>decoder -- <a href="http://fpga-dsp-scratch.blogspot.com/2008/08/vhdl-part-26-decoder.html">VHDL Part 26</a></div><div><br /></div><div>What I will write here now is the way I package my components and then proceed to the topblock. I will not make use of generics here.</div><div><br /></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px; font-size:13px;"><span style="color: rgb(51, 255, 51); ">----------------------------------------------------------------------------------------------------------</span><br /><span style="color: rgb(51, 102, 255); ">library </span><span style="color: rgb(204, 51, 204); ">IEEE;</span><br /><span style="color: rgb(51, 102, 255); ">use </span><span style="color: rgb(204, 51, 204); ">IEEE</span>.<span style="color: rgb(204, 51, 204); ">STD_LOGIC_1164</span>.<span style="color: rgb(204, 51, 204); ">ALL</span>;<br /><span style="color: rgb(51, 102, 255); ">use </span><span style="color: rgb(204, 51, 204); ">IEEE</span>.<span style="color: rgb(204, 51, 204); ">STD_LOGIC_ARITH</span>.<span style="color: rgb(204, 51, 204); ">ALL</span>;<br /><span style="color: rgb(51, 102, 255); ">use </span><span style="color: rgb(204, 51, 204); ">IEEE</span>.<span style="color: rgb(204, 51, 204); ">STD_LOGIC_UNSIGNED</span>.<span style="color: rgb(204, 51, 204); ">ALL</span>;</span><br /></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;"><br /></span></div><div><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 102, 255);">package </span></span><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;">component1 </span><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 102, 255);">is</span></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;"><br /></span></div><div><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 204, 0);">-- *********************</span></span></div><div><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 204, 0);">-- here's the 4-bit register</span></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 204, 0);">-- *********************</span></span></div><div><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 102, 255);">component </span></span><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;">ckt_reg </span><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 102, 255);">is</span></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px; font-size:13px;"><span style="color: rgb(51, 102, 255); ">Port </span>( clk : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">STD_LOGIC</span>;<br />rst : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">STD_LOGIC</span>;<br />loadEn : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">STD_LOGIC</span>;<br />reg <span style="color: rgb(51, 102, 255); "></span>_in : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">STD_LOGIC_VECTOR<span style="color: rgb(0, 0, 0); "> (regCount-1 downto 0)</span></span><span style="color: rgb(0, 0, 0); ">;</span><br />reg <span style="color: rgb(51, 102, 255); "></span>_out : <span style="color: rgb(51, 102, 255); ">out </span><span style="color: rgb(204, 51, 204); ">STD_LOGIC_VECTOR</span><span style="color: rgb(204, 51, 204); "> <span style="color: rgb(0, 0, 0); ">(regCount-1 downto 0)</span></span>);<br /><span style="color: rgb(51, 102, 255); ">end </span><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">component</span>;</span><br /></div><div><br /></div><div><div><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 204, 0); ">-- **************************</span></span></div><div><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 204, 0); ">-- here's the 4-bit shift register</span></span></div><div><span class="Apple-style-span" style="color: rgb(51, 204, 0); line-height: 20px;font-size:13px;">-- **************************<br /></span></div><div><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">component </span></span><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px; font-size:13px;">shiftReg </span><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">is</span></span></div><div><span class="Apple-style-span" style="color: rgb(51, 102, 255); line-height: 20px;font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 51, 51); "><span style="color: rgb(51, 102, 255); ">Port </span>( clk : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">STD_LOGIC</span>;<br />rst : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">STD_LOGIC</span>;<br />shiftEn : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">STD_LOGIC</span>;<br />sh_in : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">STD_LOGIC</span>;<br />shReg <span style="color: rgb(51, 102, 255); "></span>_in : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">STD_LOGIC_VECTOR<span style="color: rgb(0, 0, 0); "> (3 </span><span style=""><span class="Apple-style-span" style="color: rgb(51, 102, 255);">downto </span></span><span style="color: rgb(0, 0, 0); ">0)</span></span><span style="color: rgb(0, 0, 0); ">;</span><br />shReg <span style="color: rgb(51, 102, 255); "></span>_out : <span style="color: rgb(51, 102, 255); ">out </span><span style="color: rgb(204, 51, 204); ">STD_LOGIC_VECTOR</span><span style="color: rgb(204, 51, 204); "> <span style="color: rgb(0, 0, 0); ">(3 <span class="Apple-style-span" style="color: rgb(51, 102, 255); ">downto </span>0)</span></span>);<br /><span style="color: rgb(51, 102, 255); ">end </span><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">component</span>;<br /></span></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;"><br /></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); line-height: normal; font-size:16px;"><div><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 204, 0); ">-- *****************</span></span></div><div><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 204, 0); ">-- here's the encoder</span></span></div><div><span class="Apple-style-span" style="color: rgb(51, 204, 0); line-height: 20px; font-size:13px;">-- *****************<br /></span></div><div><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">component </span><span class="Apple-style-span" style="color: rgb(51, 51, 51);">encode1 </span></span><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">is</span></span></div><div><span class="Apple-style-span" style="color: rgb(51, 102, 255); line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 51, 51); "><span style="color: rgb(51, 102, 255); ">Port </span>( enc_in : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">std_logic_vector</span> (3 <span style="color: rgb(51, 102, 255); ">downto </span>0);<br />enc_out : <span style="color: rgb(51, 102, 255); ">out </span><span style="color: rgb(51, 102, 255); "></span><span style="color: rgb(204, 51, 204); ">std_logic_vector</span>(1 <span style="color: rgb(51, 102, 255); ">downto </span>0));<br /><span style="color: rgb(51, 102, 255); ">end </span><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">component</span>;</span></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;"><br /></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); line-height: normal; font-size:16px;"><div><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 204, 0); ">-- *****************</span></span></div><div><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 204, 0); ">-- here's the decoder</span></span></div><div><span class="Apple-style-span" style="color: rgb(51, 204, 0); line-height: 20px; font-size:13px;">-- *****************<br /></span></div><div><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">component </span><span class="Apple-style-span" style="color: rgb(51, 51, 51);">decode1 </span></span><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">is</span></span></div><div><span class="Apple-style-span" style="color: rgb(51, 102, 255); line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 51, 51); "><span style="color: rgb(51, 102, 255); ">Port </span>( clk : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">std_logic</span>;<br />rst : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">std_logic</span>;<br />dec_in : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">std_logic_vector</span> (1 <span style="color: rgb(51, 102, 255); ">downto </span>0);<br />dec_out : <span style="color: rgb(51, 102, 255); ">out </span><span style="color: rgb(51, 102, 255); "></span><span style="color: rgb(204, 51, 204); ">std_logic_vector</span>(7 <span style="color: rgb(51, 102, 255); ">downto </span>0));<br /><span style="color: rgb(51, 102, 255); ">end </span><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">component</span>;</span></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;"><br /></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;"><span style="color: rgb(51, 102, 255); ">end </span><span class="Apple-style-span" style="color: rgb(0, 0, 0);">component1</span>;<br /></span></div></span></span></div></span></span></div></div><div><span class="Apple-style-span" style="color: rgb(51, 255, 51); line-height: 20px; font-size:13px;">----------------------------------------------------------------------------------------------------------</span><br /></div><div><span class="Apple-style-span" style="color: rgb(51, 255, 51); line-height: 20px;font-size:13px;"><br /></span></div><div><span class="Apple-style-span" style="color: rgb(51, 255, 51); line-height: 20px;font-size:13px;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); line-height: normal; font-size:16px;"><div><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 204, 0); ">-- *******************************</span></span></div><div><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 204, 0); ">-- here's my topblock</span></span></div><div><span class="Apple-style-span" style="color: rgb(51, 204, 0); line-height: 20px; font-size:13px;">-- *******************************</span></div><div><span class="Apple-style-span" style="color: rgb(51, 204, 0); line-height: 20px;font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 255, 51); ">----------------------------------------------------------------------------------------------------------</span><br /></span></div><div><span class="Apple-style-span" style="color: rgb(51, 204, 0); line-height: 20px;font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 51, 51); "><span style="color: rgb(51, 102, 255); ">library </span><span style="color: rgb(204, 51, 204); ">IEEE;</span><br /><span style="color: rgb(51, 102, 255); ">use </span><span style="color: rgb(204, 51, 204); ">IEEE</span>.<span style="color: rgb(204, 51, 204); ">STD_LOGIC_1164</span>.<span style="color: rgb(204, 51, 204); ">ALL</span>;<br /><span style="color: rgb(51, 102, 255); ">use </span><span style="color: rgb(204, 51, 204); ">IEEE</span>.<span style="color: rgb(204, 51, 204); ">STD_LOGIC_ARITH</span>.<span style="color: rgb(204, 51, 204); ">ALL</span>;<br /><span style="color: rgb(51, 102, 255); ">use </span><span style="color: rgb(204, 51, 204); ">IEEE</span>.<span style="color: rgb(204, 51, 204); ">STD_LOGIC_UNSIGNED</span>.<span style="color: rgb(204, 51, 204); ">ALL</span>;</span><br /></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;"><span style="color: rgb(51, 102, 255); ">use </span><span style=""><span class="Apple-style-span" style="color: rgb(51, 102, 255);">work</span><span class="Apple-style-span" style="color: rgb(0, 0, 0);">.component1</span></span>.<span style="color: rgb(204, 51, 204); ">ALL</span>;<br /></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;"><br /></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;"><span style="color: rgb(51, 102, 255); ">entity </span><span style="">top1 </span><span style="color: rgb(51, 102, 255); ">is</span><br /><span style="color: rgb(51, 102, 255); ">port</span>(<br />clk : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">std_logic</span>;<br />rst : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">std_logic</span>;</span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;">en : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">std_logic</span>;</span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;">top_sh : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">std_logic</span>; <span class="Apple-style-span" style="color: rgb(51, 204, 0);">-- for shift register</span><br />top_in : <span style="color: rgb(51, 102, 255); ">in </span><span style="color: rgb(204, 51, 204); ">std_logic_vector</span> (1 <span style="color: rgb(51, 102, 255); ">downto </span>0);<br />top_out : <span style="color: rgb(51, 102, 255); ">out </span><span style="color: rgb(51, 102, 255); "></span><span style="color: rgb(204, 51, 204); ">std_logic_vector</span>(decWidth-1 <span style="color: rgb(51, 102, 255); ">downto </span>0)<br />);<br /></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;"><span style="color: rgb(51, 102, 255); ">end </span>top1;<br /></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;"><br /></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;"><span style="color: rgb(51, 102, 255); ">architecture </span><span style="">struct </span><span style="color: rgb(51, 102, 255); "><span class="Apple-style-span" style="color: rgb(51, 51, 51); "><span style="color: rgb(51, 102, 255); ">of </span>top1 <span style="color: rgb(51, 102, 255); ">is</span></span></span></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;"><span style="color: rgb(51, 102, 255); "><br /></span></span></div><div><span class="Apple-style-span" style="color: rgb(51, 102, 255); line-height: 20px;font-size:13px;">signal </span><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 51, 51);">tmpReg2Sh, tmpSh2Enc : <span style="color: rgb(204, 51, 204); ">std_logic_vector</span> (3 <span style="color: rgb(51, 102, 255); ">downto </span>0);</span></span></div><div><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 51, 51);"><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">signal </span>tmpEnc2Dec : <span style="color: rgb(204, 51, 204); ">std_logic_vector</span> (1 <span style="color: rgb(51, 102, 255); ">downto </span>0); </span></span></div><div><span class="Apple-style-span" style="color: rgb(51, 102, 255); line-height: 20px;font-size:13px;"><br /></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px;font-size:13px;"><span style="color: rgb(51, 102, 255); ">begin</span><br /></span></div><div><span class="Apple-style-span" style="color: rgb(51, 102, 255); line-height: 20px;font-size:13px;"><br /></span></div><div><span class="Apple-style-span" style=" line-height: 20px; font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 204, 0);">-- I will use positional mapping here</span></span></div><div><span class="Apple-style-span" style="color: rgb(51, 102, 255); line-height: 20px;font-size:13px;"><span style="color: rgb(0, 0, 0); ">COMP1 : ckt_reg </span>port map <span style="color: rgb(0, 0, 0); ">(clk, rst, en, top_in, tmpReg2Sh);</span><br /></span></div><div><span class="Apple-style-span" style=" line-height: 20px;font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 102, 255); "><span style="color: rgb(0, 0, 0); ">COMP2 : shiftReg </span>port map <span style="color: rgb(0, 0, 0); ">(clk, rst, en, top_sh, tmpReg2Sh, tmpSh2Enc);</span></span><br /></span></div><div><span class="Apple-style-span" style=" line-height: 20px;font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 102, 255); "><span style="color: rgb(0, 0, 0); ">COMP3 : encode1 </span>port map <span style="color: rgb(0, 0, 0); ">(tmpSh2Enc, tmpEnc2Dec);</span></span><br /></span></div><div><span class="Apple-style-span" style=" line-height: 20px;font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 102, 255); "><span style="color: rgb(0, 0, 0); ">COMP4 : decode1 </span>port map <span style="color: rgb(0, 0, 0); ">(clk, rst, </span></span>tmpEnc2Dec, top_out);<br /></span></div><div><span class="Apple-style-span" style=" line-height: 20px;font-size:13px;"><br /></span></div><div><span class="Apple-style-span" style=" line-height: 20px;font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 51, 51); "><span class="Apple-style-span" style="color: rgb(51, 102, 255); ">end </span>struct;</span><br /></span></div><div><span class="Apple-style-span" style=" line-height: 20px;font-size:13px;"><span class="Apple-style-span" style="color: rgb(51, 255, 51); ">----------------------------------------------------------------------------------------------------------</span></span></div><div><span class="Apple-style-span" style=" line-height: 20px;font-size:13px;"><br /></span></div><div><span class="Apple-style-span" style=" line-height: 20px;font-size:13px;">Here's the catch: I was not able to simulate this due to my tight schedule. But if there are any errors, I expect them to be minor.<br /></span></div><div><span class="Apple-style-span" style="line-height: 20px;"><br /></span></div><div><span class="Apple-style-span" style="color: rgb(51, 51, 51); line-height: 20px; font-size:13px;">References:</span><br /></div><div><span class="Apple-style-span" style="line-height: 20px;"><span class="Apple-style-span" style="color: rgb(51, 51, 51); font-size:13px;">(1) Pedroni, V., <a href="http://www.amazon.com/Circuit-Design-VHDL-Volnei-Pedroni/dp/0262162245/ref=pd_bbs_sr_1?ie=UTF8&s=books&qid=1219546493&sr=8-1" style="color: rgb(51, 102, 136); text-decoration: none; ">Circuit Design with VHDL</a>, The MIT Press, 2004.<br />(2) <a href="http://toolbox.xilinx.com/docsan/3_1i/data/fise/xst/chap02/xst02008.htm" style="color: rgb(51, 102, 136); text-decoration: none; ">Xilinx Toolbox</a></span><br /></span></div></span></span></div>tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-11244661588192600752008-09-13T03:45:00.000-07:002008-09-13T03:48:32.060-07:00CSIE 2009 Call for PapersOoops..so sorry for posting this conference invite so late..anyway, here it is.<div><br /></div><div><span class="Apple-style-span" style="color: rgb(51, 204, 0);">----------------------------------------------------------------------------</span></div><div><span class="Apple-style-span" style="font-family: 'times new roman'; font-size: 13px; -webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px; ">2009 World Congress on Computer Science and Information Engineering<br />(CSIE 2009)<br /><br />March 31 - April 2, 2009<br />Los Angeles/Anaheim, USA<br /><br /><a href="https://mail.dlsu.edu.ph/exchweb/bin/redir.asp?URL=http://world-research-institutes.org/conferences/CSIE/2009" target="_blank">http://world-research-institutes.org/conferences/CSIE/2009</a><br /><br />CALL FOR PAPERS & EXPO<br /><br />The Los Angeles/Anaheim area is known for its many renowned<br />attractions, such as Disneyland, Universal Studios and the<br />Hollywood Walk of Fame. Very few cities in the world offer<br />as much entertainment, excitement and diversity as Los<br />Angeles/Anaheim does.<br /><br />CSIE 2009 intends to be a global forum for researchers and<br />engineers to present and discuss recent advances and new<br />techniques in computer science and information engineering.<br />CSIE 2009 consists of the following Technical Symposiums:<br /><br /> * Communications & Mobile Computing Symposium<br /> * Computer Applications Symposium<br /> * Computer Design & VLSI Symposium<br /> * Data Mining & Data Engineering Symposium<br /> * Intelligent Systems Symposium<br /> * Multimedia & Signal Processing Symposium<br /> * Software Engineering Symposium<br /><br />CSIE 2009 conference proceedings will be published by the IEEE<br />Computer Society and all papers in the proceedings will be<br />included in EI Compendex, ISTP, and IEEE Xplore.<br /><br />In addition to research papers, CSIE 2009 also seeks exhibitions<br />of modern products and equipment for computer science and<br />information engineering.<br /><br />Important Dates:<br /><br />Paper/Abstract Submission Deadline: September 30, 2008<br />Review Notification: November 15, 2008<br />Final Papers and Author Registration Deadline: December 7, 2008<br /><br />Organizing Committee:<br /><br />General Chair:<br />Adrian Martin, World Research Institutes, USA<br /><br />Program Chair:<br />Mark Burgin, University of California at Los Angeles, USA<br /><br />Symposium Chairs:<br />Chan H. Ham, University of Central Florida, USA<br />Simone Ludwig, University of Saskatchewan, Canada<br />Weilian Su, Naval Postgraduate School, USA<br />Sumanth Yenduri, University of Southern Mississippi, USA<br /><br />Publicity Chair:<br />Nitin Upadhyay, Birla Institute of Technology and Science<br />(BITS), India<br /><br /><br />(Please forward to those who may be interested.)</span><br /></div>tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-34681555640418520022008-09-13T01:08:00.000-07:002008-09-13T01:29:22.839-07:00VHDL Part 39 : Packages in VHDLI am now studying how to create packages in VHDL. Packages contain common design modules that I can use in VHDL source codes. By 'common design modules', I am referring to components, functions and procedures. Components I know so I will start on this. Structural programming has done me good in my past VHDL designs since it gives me a much cleaner look and modularity. But it can be very exhausting for me especially whenever I am instantiating several components again and again. This often happens to me since I do not delete my code revisions. I can do copy-paste in component declarations; however, I want to try package and see which eases my tasks better. See you in my next post for a sample code on this trial of mine!tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0tag:blogger.com,1999:blog-1228779002887771916.post-81196146549977356532008-09-11T20:18:00.000-07:002008-09-11T20:23:59.645-07:005-meter distanceI know this is not something to wonder about in this generation. But because I love science and [Einstein is here], I decided to post this.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjglKWeZEYV9a5d8zypPubArw-nKphbMWr_LGP93zMYuQ2VDij2hu9SivG840oFAvhTCKb-0EORHQ3fZ5nKDM1a-Bs1vjZ4GUp7RC-zPwbp_isNMe2fpuQ2x-tZvZe7rl3TmtOpz-0Pxns/s1600-h/MonroeEinstein.png"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjglKWeZEYV9a5d8zypPubArw-nKphbMWr_LGP93zMYuQ2VDij2hu9SivG840oFAvhTCKb-0EORHQ3fZ5nKDM1a-Bs1vjZ4GUp7RC-zPwbp_isNMe2fpuQ2x-tZvZe7rl3TmtOpz-0Pxns/s400/MonroeEinstein.png" alt="" id="BLOGGER_PHOTO_ID_5244969761626238130" border="0" /></a><br />When you have a closer look at this picture, you see Albert Einstein.<br />When you look at it from a 5-meter distance, you see Marilyn Monroe.tahderhttp://www.blogger.com/profile/15461119866495024080noreply@blogger.com0