Timing Summary: Maximum output required time after clock

The remaining timing path domain is the Maximum output required time after clock. According to Xilinx toolbox, it is the maximum path from inputs to outputs. Gabor from Xilinx forums has a concise explanation on this.

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Quote:

..."Maximum output required time after clock" refers to the delay from the clock to external outputs of the top-level design for the worst case pins.

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Check this forum for more details.

Timing Summary: Minimum input arrival time before clock

The second domain in the Timing Summary (Design Summary, Synthesis Report) is the Minimum input arrival time before clock. Based on Xilinx toolbox, it is the maximum path from the sequential elements to all primary outputs. Again, Gabor has a very good explanation on this one.

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Quote:

"Minimum input arrival before clock" is the required setup time from the worst case top-level design input to the clock...Again after synthesis these are only estimates, you need to place and route the design to get hard numbers.  Also if your design as synthesized represents only a portion of a larger design, the input and output timings may be significantly different, as they may not represent signals going on or off of the FPGA.

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He also stressed that if the time indicated in "Minimum input arrival before clock" is less than the time in the "Minimum Period", it may be possible to run the design at the maximum clock frequency specified.

Click here to get to the source.

Timing Summary: Minimum Period

The first item in the list is the Minimum period, one of the domains of timing paths. According to Xilinx toolbox, it is the maximum path from all primary inputs to the sequential elements. One good explanation is given by, again, gszakacs in a Xilinx forum.

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Quote:

Minimum period" after synthesis is an estimate of the clock period for signals inside the design.  Thus you can invert this to get a feel for maximum clock frequency.  This is not a hard actual number, as you can only see the true numbers after place&route.  Also this may not be the actual minimum period for the design if you are limited by input and output timing.  It only calculates the worst case path timing from clock edge to clock edge for flip-flops within the design.  So if you have a path consisting of external input to flip-flop through look-up table to another flip-flop to an external output, only the path from the first flip-flop through the look-up table to the second flip-flop is measured for "Minimum period".

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He also added

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Quote:

The minimum clock period depends on paths that go from the Q output of a flip-flip to the D input of another flip-flop in the design...The worst case path may in fact not be connected at the top level.  You would need to look at a static timing report to see what the path is and whether you use it...Also note that the timing reported by synthesis is a best-guess estimate of the achievable timing after place and route.  This is usually only useful when designing reusable IP for example or some other subsystem you would like to know the possible best case speed of.   The real timing performance of a design is only known after place & route and can be found in the post P&R static timing report.  Using the advanced properties for static timing report generation you can get a verbose report that includes uncovered paths in case there are critical paths that have not been constrained.

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You may want to visit that forum.

Maximum combinational path delay: No path found

In the Design Summary, under Synthesis Report (Timing Summary heading), I always see this list:

Minimum period:

Minimum input arrival time before clock:

Maximum output required time after clock:

Maximum combinational path delay:

The last item interests me most (among the four) since it sometimes gives me this: 

Maximum combinational path delay: No path found.

I do not know whether this is good. So I checked. In a Xilinx forum, expert contributor gszakacks said,

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Quote:

This is normal if there is no path from a top-level input to a top-level output that is not clocked. I assume your design is fully pipelined, thus no combinatorial paths from input to output?

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According to a Xilinx ModelSim Simulation Tutorial from Computer and Information Science, University of Pennsylvania, 

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Quote:

Maximum combinational path delay...is the maximum delay for signal propagation in your design, so changing signals faster than [this] will result in unexpected behavior.

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They have an example there (Timing Simulation: Combinational Logic Section 2), where they made the signal transition faster which resulted in simulation failure - the output signals do not match the input signals because the inputs change too fast.

Critical Path

I heard of 'critical path' for the first time yesterday during a meeting. Our project leader was asking about an incorrect output in the main block. My teammate explained about a part in his design that is asynchronous. Then the proj leader mentioned 'critical path'. I do not know what it is so I did some reading. According to Design Recipes for FPGAs, during analysis of static timing, the delay from each input to each output of all devices is computed. The delays are then added up along each path through the circuit to get the critical path through the design. The fastest design speed is therefore obtained. The critical path is an approach to logic optimization.

Reference:

(1) Wilson, P., Design Recipes for FPGAs, 2007, pp. 40 and187, Elsevier.

Writing techware documentation

I feel so terribly burdened by having to do documentation. I had already spent 4 days with it (still counting) and I'm so slow in doing it. I know this is important in reconfigurable computing advocacy but my problem is, I'm not so good with words. I especially hate highfalutin techie words that only geeks will understand but not the common people. There. That's my problem. How do I relay such a beautiful thing as accelerated computing to young people without them being terrified that this is something they might not be able to grasp? I don't know how to start with this so I need at least a reference. I want a book that will give me just what I need. I don't want to spend too much time in writing. I want to practice coding. So I checked amazon for a guide to writing with good reviews. I saw "Writing for Computer Science" by Justin Zobel has excellent reviews (5 reviews only :)).

I'm excited to quickly read this one since it only has less than 200 pages. There's a relatively high probability I'll be able to finish this tomorrow. Hope this could speed me up and help me finish writing within this week.

Addendum (Oct. 03, 2008): 

The book is very good! I just have to finish documenting one block. Hopefully, I'll be able to go back to coding this weekend!

VHDL Code for UART (transmitter only)

I used UART to check my outputs bit-by-bit for the previous project that I did. Unfortunately, since I needed only a transmitter, the VHDL code that I have is only for the TX. I would like to settle first the answer to my question, "What is UART?" I found a very clear and simple discussion from the site of Rose-Hulman Institute of Technology. UART stands for Universal Asynchronous Receiver Transmitter. It is a parallel to serial data transmitter and a serial to parallel data receiver. The 'Asynchronous' term is there because of the fact that the clock for the UART need not be synchronized to either transmit or receive system clocks. I needed this UART to send my data outputs to my CPU's buffer and have MATLAB® check those bits. My input ports are clock, reset, my input data (from 1 to n depending on the number of outputs that I need to read, remember number of outputs not the number of bits) and of course, my output which is just a std_logic type. The simple technique my teammate taught me is to use a counter that is triggered by a synchronous enable. For example, I need to read 4 outputs from my main block. This 4 bit vectors will be fed to the input of my UART. Those 4-bit vectors are, say, 8 bits each. The first count of the counter (my UART) will be for the start bit, the next 8 contains the data, the last bit, the tenth bit will be the stop bit. The start and stop bits are necessary for every UART. This repeats for all my data. For every count, these bits will be fed to the 1-bit output. I show below a sample portion, taken from the middle of my code.

when 111=>output<='0';--this is the start bit

when  112=> output <=input10(0);

when  113=> output <=input10(1);

when  114=> output <=input10(2);

when  115=> output <=input10(3);

when  116=> output <=input10(4);

when  117=> output <=input10(5);

when  118=> output <=input10(6);

when  119=> output <=input10(7);

when  120=> output <='1';--this is the stop bit

For instance, my count ended at 120. After closing my case statement I added an if-end if statement that just says if the counter is less than 200 then increment the counter. I was adviced to have larger number for my counter. Notice that I used 200 instead of 120 as my upper limit. 

Best FPGA introductory book

Like all FPGA starters, I also struggled for a book that will serve as an FPGA tutorial. It was only this year (copyright of this book is February 2008) that I found one. This is for me (so far) the best introductory FPGA book--FPGA Prototyping by VHDL Examples, authored by Pong Chu. Learning by doing is the most effective pedagogical style and this book did not fail to deliver that one. I find Pong Chu's writing style very easy to understand because the discussions are clear. That is the most essential thing in relaying knowledge to a beginner -- clarity. That's enough for me. I don't need to say more about it.

An FPGA Application

I think one of the more promising applications of FPGA is in real-time visualization. To be able to have a solid foundation on this, I need to study graphics first or say, Digital Image Processing. I am currently reading a documentation of the Master's thesis (March 2005) entitled An FPGA-based 3D Graphics System by Niklas Knutsson of Linköping Institute of Technology. His abstract goes like this.

This report documents the work done by the author to design and implement a 3D graphic system on an FPGA (Field Programmable Gate Array). After a preamble with a background presentation to the project, a very brief introduction in computer graphics techniques and computer graphics theory is given. Then, the hardware available to the project, along with an analysis of general requirements is examined. The following chapter contains the proposed graphics system design for FPGA implementation. A broad approach to separate the design and the eventual implementation was used. Two 3D pipelines are suggested - one fully capable high-end version and one which use minimal resources. The documentation of the effort to implement the minimal graphics system previously discussed then follows. The documentation outlines the work done without going too deep into detail, and is followed by the largest of the tests conducted. Finally, chapter seven concludes the project with the most important project conclusions and some suggestions for future work. 

I am after knowing the framework of such an application since there are already lots of books that discuss the physics of real-time graphics. I find quite few papers, much less books, that discusses the implementation of image processing on FPGA.

VHDL Part 51 : Debouncer

I find debouncing circuits very handy. Not only when I checked the test vector outputs of my design, but whenever I need to use a signal's event to trigger another signal. Debouncing solves the problem I encountered whenever I use the mechanical switches in the FPGA board particularly the push buttons. Mechanical switch bounces that when I push it once,  the output could be three times the supposed signal. Good thing, I tried the Xilinx ISE 9.2i in-depth guide before, I learned that ISE has a template for a debouncer. Templates are accessed by the icon below.

On the tree at the left of the Language Templates subwindow, expand VHDL, then Synthesis Constructs > Coding Examples > Misc > Debounce Circuits. I played with the code trying to put the statement for the output within the clock statement. I also inverted the signals used to solve the output. Debouncers have been very useful to me.

VHDL Part 50 : Accessing the Serial Port

I was such in a hurry that time when I had just finished porting the search algorithm I was working on to VHDL. It ran in the FPGA board but the results I see are on the LEDs. I cannot check the output with the LEDs since they are fast even if I had set the clock so slow for me to see the transitions I still cannot read with it. To be sure, I was adviced by my teammate to read the serial port using Matlab®. My inputs will be generated by a counter that with each count, it will give the necessary inputs to my main block. To do that I first need a UART transmitter and use the push-down button on the FPGA board as my clock. In using the push-down button as the clock, I need to add a debouncing circuit to control it because one push could give several clocks. This is what I did to access the serial port on the FPGA board I am using.

VHDL Part 49 : Re Mask Generator, Third Solution

Apparently, I am not the only one that has this problem. I had found a way to solve the mask generator problem by looking in forums such as the one posted in VelocityReviews titled VHDL - generic shift register where value 'n' keeps changing. Though our circuits are different, we both struggled with mapping the generics based on an input signal. The generics have to be compiled during runtime that's why I have errors as posted on the previous post (VHDL Part 48).  What Ralph Hildebrandt suggested in that post was to model a shift register (whatever component it is) wide enough for the worst case. He also noted that all the time, those flipflops is included. It was sound enough. That is what I followed. Whatever component I/O ports you put in the FPGA board has to be fixed for obvious reasons.

VHDL Part 48 : Mask Generator, Third Solution

I cannot use the second solution. The problem with it is that the inputs have to be fixed. The mask generator that we want to do has to be flexible where  the components' ports and signals depend on the length of the input. My teammate will give me an input for the valid length then I plan to convert it to integer and use it as a parameter with which I will map my subblock generics. The problem is this method produced errors all have to do with the following:

The actual value [signal_name] associated with a generic must be a globally static expression.

I have to look for another way.

'reconfiguration' in FPGA

My teammate and I are problematic (I know he is; he doesn't know I am) about the fact that VHDL does not support reconfiguration right now. Don't get me wrong. The technology is reconfigurable by the fact that it is an FPGA board. The abstract of our project says that what's good here is the 'reconfigurability' of the board we are using when you can't actually reconfigure the board during runtime. The bright side here, as I see it, is that this is another room for study. Maybe what will happen with us is that we will implement applications and tackle the problem as we encounter it. I haven't got much time to study it all. Seems like my next two years is already programmed. I'll burn the bridge when I get there.

VHDL Part 47: Mask Generator, Second Solution

I was thinking for another solution after those posts. My project leader suggested a design that I gladly worked on. It is done by cascading an encoder, a decoder, and a register. Then having several instances of this network depending on the pattern that I want to have. My outputs are obtained from the registers. The final output is obtained by having a selector decide which output index must be taken. I'm sorry I cannot post the code here. Intellectual property man..which I am very much against.

VHDL Part 46 : Mask Generator 5

And so I said:

jeppe,

1. I hadn't tried it yet in other languages.
2. I have been using paper and pen too for this thinking I might find some other way to manipulate the flow.
3. I am just considering 3 for n and 5 for r.

I did not pursue using arrays anymore for this mask gen. (Though I was glad to be able to try vhdl arrays). The fact that I will be inferring a large amount of combinatorial circuits made me decide to switch to other possible designs. This conversation took place March this year.

VHDL Part 45 : Mask Generator 4

To which he patiently replied:

My "fast" answer without getting into details.
1) Have you tried this algoritme in other languages like C or Java.
2) Have you draw the data structures at a paper checking the flow. 
3) A got a feeling your about to create a huge combinatorial network which in the end will take up to much space.
May be should you consider a "pipelined" design in which you works at parts of the arrays. This will however cost you time instead of logic.

Jeppe

VHDL Part 44 : Mask Generator 3

I tried his code and added some lines so that I could tap a row for the output. However, I could not view the RTL schematic so I posted a follow up question.

Hi jeppe

Thank you so much for helping me. 


I had added some lines of code so that I could access a row for the output.

for j in 0 to r-1 loop
for i in 0 to n-1 loop
if maskIn_P(i) = maskIn_R(j) then
memory(i)(j) <= '1'; --THIS IS LINE 68
else
memory(i)(j) <= '0'; end if; end loop; end loop; elsif readEn = '1' then maskOut <= memory(conv_integer(address)); else maskOut <= "ZZZZZ"; end if; end if; end process; 

Here's my port declaration:

address : in STD_LOGIC_VECTOR (r-1 downto 0);
patternIn : in STD_LOGIC_VECTOR (n-1 downto 0);
referenceIn : in STD_LOGIC_VECTOR (r-1 downto 0);
maskOut : out STD_LOGIC_VECTOR (n-1 downto 0));


I got no error in checking the syntax but got one when I tried to view the RTL schematic. 
line 68: Index value <8> is not in Range of array <0>>.

I'm not sure but I have a feeling that the error is caused by this line
maskOut <= memory(conv_integer(address));

Is it necessary for n and r to be equal? I had tried letting n be equal to 8 and r to 32
but it won't synthesize. When I tried using your values which is 10 for both, it did 
synthesize. So long as n and r are equal it synthesized. But I can't have have equal values for n and r 
since my reference vector must be much longer than my pattern vector.

Thanks again,
tahder

VHDL Part 43 : Mask Generator 2

Jeppe is kind enough to answer me. Here it goes.

Hi tahder

Not sure - but I guess the generate statement not allowed inside a process.

try this instead

---------------------------------------------------------------------------------- 
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity mskgen is 
   generic( n: natural := 10; 
             r: natural := 10); 
    port( clk,maskEn: std_logic); 
end mskgen; 

architecture bhv of mskGen is 
   subtype patternArray is std_logic_vector (n-1 downto 0); 
   type referenceArray is array (r-1 downto 0) of patternArray; 
   signal memory,maskIn_P,maskIn_R : referenceArray; 

begin 
    process (clk, maskEn) 
    begin 
        if clk = '1' and clk'event then 
            if maskEn = '1' then 
                for j in 0 to r-1 loop 
                    for i in 0 to n-1 loop 
                       if maskIn_P(i)=maskIn_R(j) then 
                           memory(i)(j) <= '1'; 
                        else 
                           memory(i)(j) <= '0; 
                        end if; 
                    end loop; 
                end loop; 
            end if; 
        end if; 
    end process; 
end bhv;  

Regards
Jeppe

VHDLPart 42 : Mask Generator 1

Let me share the conversation that I had with jeppe from the vhdl forum in VelocityReviews. This is the question I posted (taht was March 2008).

Hello everyone,
I am new to vhdl and I want to implement a synthesizable mask generator. 
I thought about implementing it with a 2D array (like a ROM) that is usually seen in vhdl books.
My problem is that I'm stuck with generating the contents inside the array since an index will output a '1' only if an n-bit element is equal to another n-bit element. I don't want to have a build up of equality comparators. Is it possible to have only one comparator for the whole system? or a single row of comparators that will work for all the rows in the memory? I tried doing this:

architecture bhv of maskGen is

subtype patternArray is std_logic_vector (n-1 downto 0);
type referenceArray is array (r-1 downto 0) of patternArray;
signal memory : referenceArray;

-- this is for the magnitude comparator
component magComp
port (A, B : in std_logic_vector (n-1 downto 0);
EQ : out std_logic);
end component;

-- The behavioral architecture for magComp is only:
-- EQ <= '1' when A=B else '0'; begin process (rst, clk, maskEn) begin if clk = '1' and clk'event then if maskEn = '1' then for j in 0 to r-1 loop for i in 0 to n-1 generate -- this is line 69 magComp port map (A=>maskIn_P(i), B=>maskIn_R(j), EQ => memory(i)(j));
end generate;
end loop;
end if;
end if;

end process;
end bhv;


However, this gave me an error:
Line 69. parse error, unexpected GENERATE, expecting LOOP.

Can anyone explain why the code generated such an error? 

I really do not want to implement the code above since it might result to horrendous amount of logic.
What do I do now? 

Thanks,
tahder