VHDL Part 22 : VHDL Loops

Two loops used in software are also available in VHDL. Loops are sequential so it can be included in a process.

(1) for-loop

The for-loop is used if the designer knows when the loop must end. Syntax is shown below.

---------------------------------------------------------------------
loop_label : for loop_indentifier in loop_range loop

sequential_code

end loop loop_label;
---------------------------------------------------------------------

The loop_range can be expressed as to or downto. See this VHDL Part 12.

loop_label(s) are good for debugging especially if you have several loops in the code.

(2) while-loop

While loop is employed if the designer does not know when the fixed number of iteration a loop must perform. He only knows the condition that must be met in order to get out of the loop. Since while-loops is not usually employed in the codes that you will see here, I will be very shallow with this. Syntax is shown below.

---------------------------------------------------------------------
loop_label : while loop_condition loop -- example : while (j <>

sequential_code

end loop loop_label;
---------------------------------------------------------------------

Reference:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.