VHDL Part 12 : Shift Register IV

I had learned another way of implementing a shift register whose functionality is the same as that of the previous post. This time, however, I used the for-loop. I think this will stop with this code for shift registers. I thank Xilinx again for teaching many how to do this.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shiftReg is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
shiftEn : in STD_LOGIC;-- enable
sh_in : in STD_LOGIC;
sh_out : out STD_LOGIC);
end shiftReg;


architecture Behavioral of shiftReg is

begin

process (rst, clk)
-- I alloted 5 bits as the length of the bits' bank; replace 4 with the number you want
variable sh_v : std_logic_vector (4 downto 0)
begin

if rst = '1' then

-- initialize the output and the variable to 0
sh _out <= '0'; sh_v := (others => '0');

elsif clk'event and clk = '1' then
if shiftEn = '1' then

------------------------------------------------------
-- for shift-right register
for i in 3 downto 0 loop

sh_v (i) := sh_v(i+1); end loop;

sh_v(4) := sh_in; ------------------------------------------------------

------------------------------------------------------
-- for shift-left register, use the ff.
-- for i in 0 to 3 loop
-- sh_v (i+1) <= sh_v(i);
-- end loop;
-- sh_v(0) <= sh_in;
------------------------------------------------------
end if;
end if;

-- the statement below is for shift-right register
sh_out <= sh_v(0); -- for shift-left register replace the statement above with: sh _out <= sh_v (4);

end process;
end Behavioral;
------------------------------------------------------------------

This just shifts the input by one clock cycle.

Reference:
(1) Xilinx Shift Register Toolbox