Monday, August 18, 2008

VHDL Part 13 : A Simple Counter

In a counter, the destination and the first operand is a signal or variable and the other operand is a constant equal to 1.
- Xilinx

I really do not know what reference I must cite for this since all the books I had read include codes for counters. I think my previous posts' references will do. The code I had written below is for an up counter the output of which increments the input by one for every rising edge of the clock. The counter will be set back to zero whenever the asynchronous reset is high or the counter has reached decimal 16. Note the assignment operator := for variable. I made use of variable count_v since I cannot put the output count_out on the right side of the assignment operator (count_v := count_v + 1;). The next if-then-else statement takes care of setting count_out back to zero. I cannot go beyond decimal 15 because of the constraint I had assigned the output port with (integer range 0 to 15).

library IEEE;

entity upCounter is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
countEn : in STD_LOGIC;-- enable
count_in : in STD_LOGIC;
count_out : out INTEGER RANGE 0 To 15);
end upCounter;

architecture Behavioral of upCounter is


process (rst, clk)

variable count_v : integer range 0 to 16;


-- async reset
if rst = '1' then

-- initialize the output and the variable to 0
count _out := 0;
count_v := 0;

clk'event and clk = '1' then
if countEn = '1' then

count_v := count_v + 1;

if count_v = 16 then

count_v := 0;

end if;
end if;
end if;

count_out <= count_v;

end process;
end Behavioral;


(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.
(2) Pellerin, D. and Taylor, D., VHDL Made Easy, Prentice Hall PTR, 1996.

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