VHDL Part 17 : Wait Statements

Wait was introduced in my previous post. Since the sensitivity list is taken away, the wait statement is placed right after the begin of the process. To stress further, it must be the first statement on the body of the process. It takes three forms.

(1) wait until condition_here

wait until can take only one signal. As in my previous post, below is the wait statement that was used.

-----------------------------------------------------------------
wait until (clk'event and clk = '1')
-----------------------------------------------------------------

The above syntax of wait makes all the other signal(s) synchronous. Even if only the clk signal is taken by the wait statement, the process will still be sensitive to rst or some other signal(s). It is just that all events will respect the clock.

(2) wait on signal_1, signal_2, ...

Use wait on if you want to maintain rst (or other signals) as asynchronous. wait on can take several signals. An example is shown below.

-----------------------------------------------------------------
process --no sensitivity list
begin

wait on (rst, clk)
if rst = '1' then

shReg _out <= (others => '0');

elsif clk'event and clk = '1' then
if shiftEn = '1' then

shReg _out <= sh_in & shReg_in (regCount-1 downto 1);

end if;
end if;
end process;
-----------------------------------------------------------------

(3) wait for specific_time

wait for is commonly seen in testbenches. This is good for generating the intended waveforms at a specific time. An example is shown below. This can be a portion of a testbench.

-----------------------------------------------------------------
process --no sensitivity list
begin

rst <= '0'; shiftEn <= '1'; sh_in <= "00011"; wait for 200 ns;

shiftEn <= '0'; wait for 500 ns;

end process;
-----------------------------------------------------------------

Reference:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.