Timing Summary: Maximum output required time after clock

The remaining timing path domain is the Maximum output required time after clock. According to Xilinx toolbox, it is the maximum path from inputs to outputs. Gabor from Xilinx forums has a concise explanation on this.

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Quote:

..."Maximum output required time after clock" refers to the delay from the clock to external outputs of the top-level design for the worst case pins.

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Check this forum for more details.

Timing Summary: Minimum input arrival time before clock

The second domain in the Timing Summary (Design Summary, Synthesis Report) is the Minimum input arrival time before clock. Based on Xilinx toolbox, it is the maximum path from the sequential elements to all primary outputs. Again, Gabor has a very good explanation on this one.

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Quote:

"Minimum input arrival before clock" is the required setup time from the worst case top-level design input to the clock...Again after synthesis these are only estimates, you need to place and route the design to get hard numbers.  Also if your design as synthesized represents only a portion of a larger design, the input and output timings may be significantly different, as they may not represent signals going on or off of the FPGA.

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He also stressed that if the time indicated in "Minimum input arrival before clock" is less than the time in the "Minimum Period", it may be possible to run the design at the maximum clock frequency specified.

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Timing Summary: Minimum Period

The first item in the list is the Minimum period, one of the domains of timing paths. According to Xilinx toolbox, it is the maximum path from all primary inputs to the sequential elements. One good explanation is given by, again, gszakacs in a Xilinx forum.

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Minimum period" after synthesis is an estimate of the clock period for signals inside the design.  Thus you can invert this to get a feel for maximum clock frequency.  This is not a hard actual number, as you can only see the true numbers after place&route.  Also this may not be the actual minimum period for the design if you are limited by input and output timing.  It only calculates the worst case path timing from clock edge to clock edge for flip-flops within the design.  So if you have a path consisting of external input to flip-flop through look-up table to another flip-flop to an external output, only the path from the first flip-flop through the look-up table to the second flip-flop is measured for "Minimum period".

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He also added

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The minimum clock period depends on paths that go from the Q output of a flip-flip to the D input of another flip-flop in the design...The worst case path may in fact not be connected at the top level.  You would need to look at a static timing report to see what the path is and whether you use it...Also note that the timing reported by synthesis is a best-guess estimate of the achievable timing after place and route.  This is usually only useful when designing reusable IP for example or some other subsystem you would like to know the possible best case speed of.   The real timing performance of a design is only known after place & route and can be found in the post P&R static timing report.  Using the advanced properties for static timing report generation you can get a verbose report that includes uncovered paths in case there are critical paths that have not been constrained.

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You may want to visit that forum.