Timing Summary: Minimum input arrival time before clock

The second domain in the Timing Summary (Design Summary, Synthesis Report) is the Minimum input arrival time before clock. Based on Xilinx toolbox, it is the maximum path from the sequential elements to all primary outputs. Again, Gabor has a very good explanation on this one.

---

Quote:

"Minimum input arrival before clock" is the required setup time from the worst case top-level design input to the clock...Again after synthesis these are only estimates, you need to place and route the design to get hard numbers.  Also if your design as synthesized represents only a portion of a larger design, the input and output timings may be significantly different, as they may not represent signals going on or off of the FPGA.

---

He also stressed that if the time indicated in "Minimum input arrival before clock" is less than the time in the "Minimum Period", it may be possible to run the design at the maximum clock frequency specified.

Click here to get to the source.