Critical Path

I heard of 'critical path' for the first time yesterday during a meeting. Our project leader was asking about an incorrect output in the main block. My teammate explained about a part in his design that is asynchronous. Then the proj leader mentioned 'critical path'. I do not know what it is so I did some reading. According to Design Recipes for FPGAs, during analysis of static timing, the delay from each input to each output of all devices is computed. The delays are then added up along each path through the circuit to get the critical path through the design. The fastest design speed is therefore obtained. The critical path is an approach to logic optimization.

Reference:

(1) Wilson, P., Design Recipes for FPGAs, 2007, pp. 40 and187, Elsevier.