VHDL Part 26 : Decoder

Although I had already implemented a decoder in VHDL Part 20, it is worth tackling this circuit once more. I had shown below a sample code. I need a decoder for the current ___ generator I'm working on. Sorry guys, I can't tell you about it.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decode1 is
generic (decWidth : natural := 8);
port(
clk : in std_logic;
rst : in std_logic;
dec_in : in std_logic_vector (1 downto 0);
dec_out : out std_logic_vector(decWidth-1 downto 0)
);
end decode1;

architecture Behavioral of decode1 is
begin
process (clk, rst)
begin

if rst = '1' then

dec_out <= (others => 'Z');

elsif clk'event and clk = '1' then

case dec_in is

when "11" => dec_out <= "01100001"; -- a
when "10" => dec_out <= "01100011"; -- c
when "01" => dec_out <= "01110100"; -- t
when others => dec_out <= "01100111"; -- g
end case;
end if;
end process;
end Behavioral;
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The circuit I had used has two typical one-bit inputs clk and rst. Another input dec_in (2 bits) is used to select which of the four bit vectors must be passed to the output port dec_out(8 bits). The output may represent any of the four letters a, c, t and g. The selector dec_in is represented by only two bits because there are only four possible outputs (2**2 = 4). The 8-bit vectors are the ASCII representation of the letters.