Maximum combinational path delay: No path found

In the Design Summary, under Synthesis Report (Timing Summary heading), I always see this list:

Minimum period:

Minimum input arrival time before clock:

Maximum output required time after clock:

Maximum combinational path delay:

The last item interests me most (among the four) since it sometimes gives me this: 

Maximum combinational path delay: No path found.

I do not know whether this is good. So I checked. In a Xilinx forum, expert contributor gszakacks said,

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Quote:

This is normal if there is no path from a top-level input to a top-level output that is not clocked. I assume your design is fully pipelined, thus no combinatorial paths from input to output?

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According to a Xilinx ModelSim Simulation Tutorial from Computer and Information Science, University of Pennsylvania, 

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Quote:

Maximum combinational path delay...is the maximum delay for signal propagation in your design, so changing signals faster than [this] will result in unexpected behavior.

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They have an example there (Timing Simulation: Combinational Logic Section 2), where they made the signal transition faster which resulted in simulation failure - the output signals do not match the input signals because the inputs change too fast.