Saturday, October 4, 2008

Timing Summary: Maximum output required time after clock

The remaining timing path domain is the Maximum output required time after clock. According to Xilinx toolbox, it is the maximum path from inputs to outputs. Gabor from Xilinx forums has a concise explanation on this.

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Quote:

..."Maximum output required time after clock" refers to the delay from the clock to external outputs of the top-level design for the worst case pins.
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Check this forum for more details.

1 comment:

N3t0 said...

hi, just a little comment, I notice that the title is "Timing Sumary: Maximum output required time -before- clock", and the explanation and the result of Xilinx is the "Maximum output required time -AFTER- clock".
I hope I´m not getting mistake, but if I did´t I apologyze.

Greets.
N3t0