Learning accelerated computing and digital signal processing from the very beginning.
Saturday, October 4, 2008
Timing Summary: Maximum output required time after clock
The remaining timing path domain is the Maximum output required time after clock. According to Xilinx toolbox, it is the maximum path from inputs to outputs. Gabor from Xilinx forums has a concise explanation on this.
..."Maximum output required time after clock" refers to the delay from the clock to external outputs of the top-level design for the worst case pins.
“...it is impossible to explain honestly the beauties of the laws of nature in a way that people can feel, without their having some deep understanding of mathematics. I am sorry, but this seems to be the case." - R Feynman