Tuesday, August 5, 2008

VHDL Part 5: n-bit Register

Today, I tried implementing an-bit register in vhdl that functions much the same way as d-flipflop but the number of bits for data ports I had increased from 1 to n. I replace std_logic with std_logic_vector. My references are listed at the bottom of this post.

library IEEE;

entity ckt_reg is
generic (pattern : natural := 4);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
loadEn : in STD_LOGIC;
reg _in : in STD_LOGIC_VECTOR (regCount-1 downto 0);
reg _out : out STD_LOGIC_VECTOR (regCount-1 downto 0));
end ckt_reg ;

architecture Behavioral of ckt_reg is

(clk, rst)

if rst = '1' then

reg _out <= '0';

clk'event and clk = '1' then
if loadEn = '1' then

reg _out <= reg_in;

end if;
end if;
end process;

end Behavioral;

generic (regCount : natural := 4);
-- generic is a way to specify a static parameter. It is good for flexibility and reusability. For the code above n is 4. To change the port size, do the editing in the generic statement.
Syntax is

generic (generic_name : generic_type := generic_value);

Generic types can be any predefined numeric subtypes like integer, natural, positive, etc.

reg _in : in STD_LOGIC_VECTOR (regCount-1 downto 0);
-- reg_in is declared as a 4-bit vector with the leftmost bit as the MSB. if you want the rightmost bit to be the MSB, use: (0 to regCount-1).

Simulation Results
Here's my simulation results. The is set at 3000 ns.

(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.
(2) Pellerin, D. and Taylor, D., VHDL Made Easy, Prentice Hall PTR, 1996.

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