VHDL Part 10 : n-bit Shift-Right/Shift-Left Register

I found another way of implementing an n-bit shift-right/left register. I replaced the n in the generic declaration with the number I want. I used the concatenation operator to push the bits to the right and drop the LSB.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shiftReg is
generic (regCount : natural := n); -- replace n with 4, 5, 8, etc. depends on the number you need
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
shiftEn : in STD_LOGIC;
sh_in : in STD_LOGIC;
shReg _in : in STD_LOGIC_VECTOR (regCount-1 downto 0);
shReg _out : out STD_LOGIC_VECTOR (regCount-1 downto 0));
end shiftReg;


architecture Behavioral of shiftReg is

begin

process (rst, clk)
begin

if rst = '1' then

shReg _out <= (others => '0');

elsif clk'event and clk = '1' then
if shiftEn = '1' then

-- the statement below is for shift-right register; for shift-left register, replace the statement below with: shReg _out <= shReg_in (regCount-2 downto 0) & sh_in;
shReg _out <= sh_in & shReg_in (regCount-1 downto 1);

end if;
end if;
end process;

end Behavioral;
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When reset is high, the output shReg_out is reset to 0. I used (others=>'0') to fill the bit vector up with logic 0s. This is a good practice especially if the length of the bit vector is very long. On the rising edge of the clock, the code performs the necessary shift.

Unlike the previous post where I just used fixed bit '1' (or '0') to push the bits to the right, here I used an external input (sh_in) that will shift the bit vectors (shReg_in) either to the right or to the left. Please take note of the boundaries of shReg_in in the code. I had dropped the MSB for shift-left or the LSB for shift-right. & is the concatenation operator. I did not use any signals here.