VHDL Part 19 : Counter with integer to std_logic_vector Converter

I learned to implement a counter but this time the input and output ports are bit vectors. I had done this with the goal of eventually connecting this to a seven segment decoder. This is so that I can use a seven segment display as an output device.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter3 is
generic (coutWidth : natural := 4);
port(clk : in STD_LOGIC;
rst : in STD_LOGIC;
set : in STD_LOGIC;
countEn : in STD_LOGIC;
count_out : in STD_LOGIC_VECTOR (coutWidth-1 downto 0));
end counter3;

architecture Behavioral of counter3 is
begin

process (clk, rst, set, countEn)

variable count_v : integer range 0 to 15;

-- start_c is default, we want this to be the number the counter will start with
constant start_c : integer range 0 to 15 := 3;

begin
if rst = '1' then
count_v := 0;
elsif clk'event and clk = '1' then
if countEn = '1' and set = '1' then
count_v := start_c;
elsif countEn = '1' and set = '0' then
if count_v = 15 then
count_v := start_c;
else
count_v := count_v + 1 ;
end if;
end if;
end if;

case count_v is
when 0 => count_out <= "0000";
when 1 => count_out <= "0001";
when 2 => count_out <= "0010";
when 3 => count_out <= "0011";
when 4 => count_out <= "0100";
when 5 => count_out <= "0101";
when 6 => count_out <= "0110";
when 7 => count_out <= "0111";
when 8 => count_out <= "1000";
when 9 => count_out <= "1001";
when 10 => count_out <= "1010";
when 11 => count_out <= "1011";
when 12 => count_out <= "1100";
when 13 => count_out <= "1101";
when 14 => count_out <= "1110";
when others=> count_out <= "1111";
end case;
end process;
end Behavioral;
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Reference:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.