VHDL Part 25 : Accumulator

In an accumulator, the destination and first operand is a signal or variable, and the second operand is either another signal or variable or a constant not equal to 1.
- Xilinx

The statement above actually expresses the difference between a counter and an accumulator. A counter increments a signal or variable only by 1. With accumulator I can increment a signal/variable with any number. I had modified the counter code in VHDL Part 13 to implement an accumulator in VHDL. Special thanks to Xilinx toolbox for their tutorial on this. Link is at the bottom of this page

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity accu1 is
generic (accuWidth : natural := 4);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
accuEn : in STD_LOGIC;-- enable
accu_in : in STD_LOGIC_VECTOR (accuWidth-1 downto 0);
accu_out : out STD_LOGIC_VECTOR (accuWidth-1 downto 0));
end accu1;


architecture Behavioral of accu1 is

begin

process (rst, clk)

-- note that we can have a bit vector for a variable
variable accu_v : STD_LOGIC_VECTOR (accuWidth-1 downto 0);

begin

-- async reset
if rst = '1' then

-- initialize the output and the variable to "0..."
accu_out <= (others=>'0');
accu_v := (others=>'0');

elsif clk'event and clk = '1' then
if accuEn = '1' then

accu_v := accu_v + accu_in;

end if;
end if;
accu_out <= accu_v;
end process;
end Behavioral;
------------------------------------------------------------------

Reference:
(1) Xilinx Accumulator Toolbox