Tuesday, August 12, 2008

VHDL Part 9 : Shift Register

I had been integrating shift registers in my designs since the algorithm calls for them. I found out, again, that there are a lot of ways by which one can implement a shift register. Let me present one. The n-bit shift register I had written below has an asynchronous reset, a positive-edge clock, serial in and serial out. Of course, I cannot do this without the guide of my friendly references listed at the bottom of this post.

library IEEE;

entity shiftReg is
generic (
regCount : natural := 5);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
loadEn : in STD_LOGIC;
shiftEn : in STD_LOGIC;
shReg _in : in STD_LOGIC_VECTOR (regCount-1 downto 0);
shReg _out : out STD_LOGIC_VECTOR (regCount-1 downto 0));
end shiftReg;

architecture Behavioral of shiftReg is

component ckt_reg
port (clk, rst, loadEn
: in std_logic;
reg _in : in STD_LOGIC_VECTOR (regCount-1 downto 0);
reg _out : out STD_LOGIC_VECTOR (regCount-1 downto 0));
end component;

signal tmpShift : std_logic_vector (regCount-1 downto 0);


iReg : ckt_reg port map (clk=>clk, rst=>rst, loadEn=>loadEn,
reg_in=>shReg_in, reg_out=>tmpShift);

shReg_out <= '1' & tmpShift (regCount -1 downto 1) when shiftEn = '1' else shReg_in;

end Behavioral;

The regular declarations are shown above and made use of 'natural' and 'signal'--things that were discussed on my previous posts.

My code above took advantage of the highly concurrent nature of vhdl. I had used a 5-bit register that uses the d-flipflop (see VHDL Part 6). To call this circuit into the shift register, on the sources subwindow, highlight the topblock shiftReg then on the Processes subwindow, Add Existing Source. Locate the files ckt_reg.vhd and dFF.vhd. Double click them to open them in the current source shiftReg. Or on the Sources subwindow, right click the topblock and select Add Source... then locate the files and double click them. I had used a signal tmpShift to temporarily store the output of ckt_reg. I cannot map reg_out to shReg_out and then do this:

shReg_out <= '1' & shReg_out(regCount -1 downto 1) when shiftEn = '1' else shReg_in;

which is very much like what is done in software programming since this will pose an error when I do Check Syntax:

ERROR:HDLParsers:1401 - "file_path_here" Line line_#. Object shReg_out of mode OUT can not be read.

This Check Syntax error simply states that I cannot place an output port on the right side of the assignment operator (should always be output<=input). After port mapping ckt_reg, the code below follows
shReg_out <= '1' & tmpShift(regCount -1 downto 1) when shiftEn = '1' else shReg_in;

which tells vhdl that when shiftEn is high to use '1' to push the bits to the right (note that I had used the concatenation operator &) and drop the LSB of the ckt_reg output since the output port is constrained to 5 bits. If shiftEn is low, as indicated by else, pass the input shReg_in to the output.

Shown below is my simulation results.
My simulation ends at 2000ns.

The input shReg_in is loaded into ckt_reg and shifted when clock is high and enables loadEn and shiftEn is high.

(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.
(2) Pellerin, D. and Taylor, D., VHDL Made Easy, Prentice Hall PTR, 1996.

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