VHDL Part 47: Mask Generator, Second Solution

I was thinking for another solution after those posts. My project leader suggested a design that I gladly worked on. It is done by cascading an encoder, a decoder, and a register. Then having several instances of this network depending on the pattern that I want to have. My outputs are obtained from the registers. The final output is obtained by having a selector decide which output index must be taken. I'm sorry I cannot post the code here. Intellectual property man..which I am very much against.

VHDL Part 40 : Declaring Components in Packages

If I use a code as a component, I can then use it in another circuit which allows me to create designs in hierarchy. I find this good since it enables code reusability. However, I find it tiring to declare codes/components again and again everytime I revise my topblock. I sometimes place these components in a library so that I can do away with explicitly writing such codes.

For instance I need to instantiate a shift register, 4-bit  register, a decoder and an encoder. So first I have to create individual codes for each of these 4 circuits. You may see my previous posts for their sample codes. 

4-bit register -- VHDL Part 5

shift register -- VHDL Part 10

encoder -- VHDL Part 29

decoder -- VHDL Part 26

What I will write here now is the way I package my components and then proceed to the topblock. I will not make use of generics here.

----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

package component1 is

-- *********************

-- here's the 4-bit register

-- *********************

component ckt_reg is

Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
loadEn : in STD_LOGIC;
reg _in : in STD_LOGIC_VECTOR (regCount-1 downto 0);
reg _out : out STD_LOGIC_VECTOR (regCount-1 downto 0));
end component;

-- **************************

-- here's the 4-bit shift register

-- **************************

component shiftReg is

Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
shiftEn : in STD_LOGIC;
sh_in : in STD_LOGIC;
shReg _in : in STD_LOGIC_VECTOR (3 downto 0);
shReg _out : out STD_LOGIC_VECTOR (3 downto 0));
end component;

-- *****************

-- here's the encoder

-- *****************

component encode1 is

Port ( enc_in : in std_logic_vector (3 downto 0);
enc_out : out std_logic_vector(1 downto 0));
end component;

-- *****************

-- here's the decoder

-- *****************

component decode1 is

Port ( clk : in std_logic;
rst : in std_logic;
dec_in : in std_logic_vector (1 downto 0);
dec_out : out std_logic_vector(7 downto 0));
end component;

end component1;

----------------------------------------------------------------------------------------------------------

-- *******************************

-- here's my topblock

-- *******************************

----------------------------------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

use work.component1.ALL;

entity top1 is
port(
clk : in std_logic;
rst : in std_logic;

en : in std_logic;

top_sh : in std_logic; -- for shift register
top_in : in std_logic_vector (1 downto 0);
top_out : out std_logic_vector(decWidth-1 downto 0)
);

end top1;

architecture struct of top1 is

signal tmpReg2Sh, tmpSh2Enc :  std_logic_vector (3 downto 0);

signal tmpEnc2Dec :  std_logic_vector (1 downto 0); 

begin

-- I will use positional mapping here

COMP1 : ckt_reg port map (clk, rst, en, top_in, tmpReg2Sh);

COMP2 : shiftReg port map (clk, rst, en, top_sh, tmpReg2Sh, tmpSh2Enc);

COMP3 : encode1 port map (tmpSh2Enc, tmpEnc2Dec);

COMP4 : decode1 port map (clk, rst, tmpEnc2Dec, top_out);

end struct;

----------------------------------------------------------------------------------------------------------

Here's the catch: I was not able to simulate this due to my tight schedule. But if there are any errors, I expect them to be minor.

References:

(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.
(2) Xilinx Toolbox

VHDL Part 37 : Finite State Machine Sample Design Code

I had already illustrated the states I want my signals to go through. I have learned that to be able to design a state machine, I need one combinational and one sequential processes. So now I need to code it.

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fsm1 is
port(
clk : in std_logic;
rst : in std_logic;
cond_1 : in std_logic;
cond_2 : in std_logic;
block1_en : out std_logic;
block2_en : out std_logic;
block3_en : out std_logic;
block4_en : out std_logic);
end fsm1;

architecture Behavioral of fsm1 is

-- let me declare my states by enumeration; the present state and next states as signals, the
-- data type of which is my list of states (fsmState)
type fsmState is (idleState, state1, state2, state3, state4);
signal presentState, nextState : fsmState;

begin

-- here's my sequential process
seq_process : process (clk,rst)
begin

if rst = '1' then 

-- idleState is the default state
presentState <= idleState; 

elsif clk'event and clk = '1' then 

presentState <= nextState; 

end if;
end process seq_process;

-- here's my combinational process
comb_process : process (presentState, cond_1, cond_2)
begin

case presentState is

when idleState =>

-- all my blocks are disabled
block1_en <= '0';
block2_en <= '0';
block3_en <= '0';
block4_en <= '0

-- at the next clock (as seen on the sequential process), my next state will be state 1
nextState <= state1; 

when state1 =>

-- enable only block1
block1_en <= '1';
block2_en <= '0';
block3_en <= '0';
block4_en <= '0'; 

-- conditions changed?
if ((cond_1 = '1') and (cond_2 = '0')) then

nextState <= state2;

elsif ((cond_1 = '0') and (cond_2 = '1')) then

nextState <= state3; 

else

nextState <= idleState; 

end if;

when state2 =>

-- enable only block2
block1_en <= '0'; 
block2_en <= '1'; 
block3_en <= '0'; 
block4_en <= '0'; 

-- conditions changed?
if ((cond_1 = '1') and (cond_2 = '0')) then

nextState <= state4; 

else

nextState <= state2; 

end if;

when state3 =>

-- enable only block3
block1_en <= '0'; 
block2_en <= '0'; 
block3_en <= '1'; 
block4_en <= '0'; 

-- conditions changed?
if ((cond_1 = '0') and (cond_2 = '1')) then

nextState <= state4; 

else

nextState <= state3; 

end if;

when state4 =>

-- enable only block4
block1_en <= '0'; 
block2_en <= '0';
block3_en <= '0'; 
block4_en <= '1';

-- conditions changed?
if ((cond_1 = '1') and (cond_2 = '1')) then

nextState <= state1;

else

nextState <= state4; 

end if;
end case;
end process comb_process;
end Behavioral;
----------------------------------------------------------------------------------
I did not have any warnings when I synthesized it. When I tried closing the cases in my case statement with

------------------------------
when others =>

nextState <= presentState;
------------------------------

I have the following warnings

------------------------------
WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:1294 - Latch is equivalent to a wire in block .
WARNING:Xst:1294 - Latch is equivalent to a wire in block .
WARNING:Xst:1294 - Latch is equivalent to a wire in block .
WARNING:Xst:1294 - Latch is equivalent to a wire in block .
------------------------------

Ok. I had already completed my case statement with when others. Why is it that I still have WARNING:Xst:737? After I read the warnings carefully, I noticed that ISE has given my outputs latch equivalents which I do not want because it seems to me that my outputs are not clocked. I tried adding the outputs to my when others like so

------------------------------
when others =>

block1_en <= '0'; block2_en <= '0'; block3_en <= '0'; block4_en <= '0'; nextState <= presentState;
------------------------------

The warnings then disappeared.

Yehey ;)

Reference:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.

VHDL Part 36 : Finite State Machine Sample Design Illustration

So I want to design and simulate a state machine using VHDL. First, since I am a starter, I must have an illustration of want I want my circuit to go through. I have made a very simple flow as illustrated below.

And here's what I want to happen at each state.

I then need I/O ports of course. For my inputs, I'll have clk (master clock), rst (master reset) and cond_1 and cond_2 as conditions. My outputs will be the enables of my 4 blocks.

VHDl Part 32 : Finite State Machines (FSM)

I'm back..I have been very busy these past few days coding a block that would interface a dual-port block, a software control and sdram controller. So I got lost in circulation :).

The first time I encountered FSM was when it was taught in the class. It hadn't appealed to me much since it was only a one day discussion and more on theories. We didn't actually code it. When a training in the basics of Xilinx ISE was held in our office this year, it caught my interest. I just realized how useful state machines are and so I decided to blog about it. The only book that got me going in using FSM is the one by Pedroni, V., Circuit Design with VHDL. Here's some points I got from that book.

In constructing a single FSM you need two process, one combinational and one sequential.

That's it! heheh.. Well, there are some primers the author gave like the Moore-Mealy machines. It's much better discussed by him so you just check out his book.

To better understand FSM I need to study the design samples in the book and then try to come up with my own. And that's what I will blog next!

VHDL Part 9 : Shift Register

I had been integrating shift registers in my designs since the algorithm calls for them. I found out, again, that there are a lot of ways by which one can implement a shift register. Let me present one. The n-bit shift register I had written below has an asynchronous reset, a positive-edge clock, serial in and serial out. Of course, I cannot do this without the guide of my friendly references listed at the bottom of this post.

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shiftReg is
generic (regCount : natural := 5);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
loadEn : in STD_LOGIC;
shiftEn : in STD_LOGIC;
shReg _in : in STD_LOGIC_VECTOR (regCount-1 downto 0);
shReg _out : out STD_LOGIC_VECTOR (regCount-1 downto 0));
end shiftReg;

architecture Behavioral of shiftReg is

component ckt_reg
port (clk, rst, loadEn : in std_logic;
reg _in : in STD_LOGIC_VECTOR (regCount-1 downto 0);
reg _out : out STD_LOGIC_VECTOR (regCount-1 downto 0));
end component;

signal tmpShift : std_logic_vector (regCount-1 downto 0);

begin

iReg : ckt_reg port map (clk=>clk, rst=>rst, loadEn=>loadEn, reg_in=>shReg_in, reg_out=>tmpShift);

shReg_out <= '1' & tmpShift (regCount -1 downto 1) when shiftEn = '1' else shReg_in;

end Behavioral;
------------------------------------------------------------------

The regular declarations are shown above and made use of 'natural' and 'signal'--things that were discussed on my previous posts.

My code above took advantage of the highly concurrent nature of vhdl. I had used a 5-bit register that uses the d-flipflop (see VHDL Part 6). To call this circuit into the shift register, on the sources subwindow, highlight the topblock shiftReg then on the Processes subwindow, Add Existing Source. Locate the files ckt_reg.vhd and dFF.vhd. Double click them to open them in the current source shiftReg. Or on the Sources subwindow, right click the topblock and select Add Source... then locate the files and double click them. I had used a signal tmpShift to temporarily store the output of ckt_reg. I cannot map reg_out to shReg_out and then do this:

shReg_out <= '1' & shReg_out(regCount -1 downto 1) when shiftEn = '1' else shReg_in;

which is very much like what is done in software programming since this will pose an error when I do Check Syntax:

ERROR:HDLParsers:1401 - "file_path_here" Line line_#. Object shReg_out of mode OUT can not be read.

This Check Syntax error simply states that I cannot place an output port on the right side of the assignment operator (should always be output<=input). After port mapping ckt_reg, the code below follows

shReg_out <= '1' & tmpShift(regCount -1 downto 1) when shiftEn = '1' else shReg_in;

which tells vhdl that when shiftEn is high to use '1' to push the bits to the right (note that I had used the concatenation operator &) and drop the LSB of the ckt_reg output since the output port is constrained to 5 bits. If shiftEn is low, as indicated by else, pass the input shReg_in to the output.

Shown below is my simulation results.
My simulation ends at 2000ns.

The input shReg_in is loaded into ckt_reg and shifted when clock is high and enables loadEn and shiftEn is high.

References:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.
(2) Pellerin, D. and Taylor, D., VHDL Made Easy, Prentice Hall PTR, 1996.

VHDLPart 7 : signal vs variable

I had been pondering on what the difference between a signal and a variable is. This is very important for me since I am limited by the specs of the board I am using. After reading a number of books and forums, I was able to identify the distinction between the two. Ben Cohen's book VHDL Coding Styles and Methodologies discusses this better, I think. There's also a good discussion about this on this forum. I had summarized here what I had learned. I did not put here a very technical definition. What's here is enough for me at this time. First, let me give the proper placement of the two.

------------------------------------------------------------------------------------------

architecture architecture_name of entity_name is

declare component here
declare signal here

begin

process(sensitivity_list)

declare variable here

begin

code
.
.
.
end process;
end architecture_name;

------------------------------------------------------------------------------------------

Signals and variables are object classes and not data types. A signal must be declared after architecture but before beginning the body of the architecture. It has a past state and so the simulator must have the needed data structures to remember this. Signals are similar to wires and so, component ports are signals. A variable on the other hand are local to processes and must be declared within the process. It only needs to keep the current value and so the needed data structure for this class is simpler since it does not have a history associated to it. Therefore, variables require lesser storage than signals especially during simulation where signals require a lot of overhead storage. We may say that variables are more efficient than signals; however, it still depends on the design. As stated above, the right way to connect ports is through the use of signals. I also use clocked signals for delays.

Seems to me that signal infers a register and variable infers a latch.

References:
(1) Cohen, B., VHDL Coding Styles and Methodologies, Kluwer Academic Publishers, 1995.
(2) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.
(3) Pellerin, D. and Taylor, D., VHDL Made Easy, Prentice Hall PTR, 1996.
(4) velocityreviews

VHDL Part 2 : The General Structure of a Source Code

I have been reading the book Circuit Design with VHDL by Volnei A. Pedroni. I think it is a great introductory book to vhdl. These are the things I should not forget in coding with vhdl. I had put brief summary of its general structure here. I based it on the book.

The structure of a VHDL source code has at least three main sections:

(1) LIBRARY DECLARATION
(2) ENTITY
(3) ARCHITECTURE

(1) Include in the library declaration all libraries that is needed in the design. Examples are ieee, work, std and so on.

(2) The entity declaration includes the entity name and the input and output ports of the circuit.

(3) Architecture contains the code of how the circuit should function.

References:
Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.

VHDL Part 1

From all the books I have read that discusses VHDL, its definition boils down to the following definitions.

VHDL stands for VHSIC Hardware Description Language. VHSIC is an acronym for Very High Speed Integrated Circuits, a pioneer program under the United States Department of Defense in 1980s and led to the development of VHDL. VHDL is a hardware description language that is used to describe an electronic system. Popular programming languages such as C or C++ can be used to develop a software at a high level while VHDL can be used to develop hardware using design techniques at a high level.

There are a lot of books that provide good introduction to VHDL and so I'll not spend whole time taking note of it.