VHDLPart 7 : signal vs variable

I had been pondering on what the difference between a signal and a variable is. This is very important for me since I am limited by the specs of the board I am using. After reading a number of books and forums, I was able to identify the distinction between the two. Ben Cohen's book VHDL Coding Styles and Methodologies discusses this better, I think. There's also a good discussion about this on this forum. I had summarized here what I had learned. I did not put here a very technical definition. What's here is enough for me at this time. First, let me give the proper placement of the two.

------------------------------------------------------------------------------------------

architecture architecture_name of entity_name is

declare component here
declare signal here

begin

process(sensitivity_list)

declare variable here

begin

code
.
.
.
end process;
end architecture_name;

------------------------------------------------------------------------------------------

Signals and variables are object classes and not data types. A signal must be declared after architecture but before beginning the body of the architecture. It has a past state and so the simulator must have the needed data structures to remember this. Signals are similar to wires and so, component ports are signals. A variable on the other hand are local to processes and must be declared within the process. It only needs to keep the current value and so the needed data structure for this class is simpler since it does not have a history associated to it. Therefore, variables require lesser storage than signals especially during simulation where signals require a lot of overhead storage. We may say that variables are more efficient than signals; however, it still depends on the design. As stated above, the right way to connect ports is through the use of signals. I also use clocked signals for delays.

Seems to me that signal infers a register and variable infers a latch.

References:
(1) Cohen, B., VHDL Coding Styles and Methodologies, Kluwer Academic Publishers, 1995.
(2) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.
(3) Pellerin, D. and Taylor, D., VHDL Made Easy, Prentice Hall PTR, 1996.
(4) velocityreviews