VHDL Part 28 : Comparator using when-else statement

Here, another way of implementing concurrent statements is introduced. The comparator in the previous post VHDL Part 27 is implemented using when-else statements.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity compare1 is
generic (compWidth : natural := 8);
port(
clk : in std_logic;
rst : in std_logic;
comp_in1 : in std_logic_vector (compWidth-1 downto 0);
comp_in2 : in std_logic_vector (compWidth-1 downto 0);
comp_out1 : out std_logic;
comp_out2 : out std_logic;
comp_out3 : out std_logic;
comp_out4 : out std_logic;
);
end compare1;

architecture Behavioral of compare1 is
begin

comp_out1 <= '1' when comp_in1 = comp_in2 else '0';
comp_out2 <= '1' when (comp_in1 >
comp_in2) else '0';
comp_out3 <= '1' when comp_in1 > comp_in2 else '0';
comp_out4 <= '1' when comp_in1 /= comp_in2 else '0';


end Behavioral;
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References:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.