VHDL Part 6 : n-bit register using D-flipflop

I thought maybe I can use the d-flipflop I had done before to generate an n-bit register. Guided by my usual references, I found out I can use the for-generate statement to do this. After trying to code it, I simulated and I succeeded.

Here, I had posted another way of implementing an n-bit register in vhdl. I had implemented a 4-bit register again but this time I did it by cascading 4 D-type flipflops I had posted in VHDL Part 4 using the for-generate construct.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ckt_reg is
generic (regCount : natural := 4);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
loadEn : in STD_LOGIC;
reg _in : in STD_LOGIC_VECTOR (regCount-1 downto 0);
reg _out : out STD_LOGIC_VECTOR (regCount-1 downto 0));
end ckt_reg ;

architecture Behavioral of ckt_reg is

component dFF
port (clk, rst, loadEn, D_in : in std_logic;
D_out : out std_logic);
end component;

begin

iFF : for i in 0 to regCount-1 generate
FF : dFF port map (clk=>clk, rst=>rst, loadEn=>loadEn, D_in=>reg _in(i), D_out=>reg _out(i));
end generate iFF;

end Behavioral;
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I had used the dFF. For me to call this circuit into ckt_reg, on the Sources subwindow, highlight the topblock ckt_reg then on the Processes subwindow, Add Existing Source. Locate the file dFF.vhd. Double click them to open it in the current source ckt_reg. Or on the Sources subwindow, right click the topblock and select Add Source...Then locate the file and double click it.

For-generate is a concurrent construct which allows the section enclosed to be repeated a number of times. Here, I have created 4 instances of D-flipflops.

Reference:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.