VHDL Part 18 : Initializing signals

I had encountered this warning which you have probably encountered too.

"The application failed to initialize properly..."

One way I get around this is I initialize the signal(s) or variable(s) you used. Syntax is shown below.

signal signal_name : data_type := initial_value;

--------------------------------------------------------------------
signal count_s : std_logic_vector (127 downto 0) := (others => '0');
--------------------------------------------------------------------

This special kind of assignment in which the user assigned an initial value to a signal (or variable or generic or port) is called aggregate assignment. This works only in simulation but not in synthesis. Initial values are commonly ignored by the tool you use for synthesis for reasons that the tool cannot predict that the target board will be triggered in a known state.

References:
(1) Pellerin, D. and Taylor, D., VHDL Made Easy, Prentice Hall PTR, 1996.