VHDL Part 16 : Forms of Process Statements

Whenever I use if-then-else statements, I use Process statements. This is for me to be able to simulate the response of the output for a change in the inputs it is sensitive to. Process statements can have two forms--with sensitivity list and without.

The codes I had used in the previous posts are processes with sensitivity list. During simulation, these processes execute whenever any signal in my sensitivity list changes.

-----------------------------------------------------------------
process (rst, clk)
begin

if rst = '1' then

shReg _out <= (others => '0');

elsif clk'event and clk = '1' then
if shiftEn = '1' then

shReg _out <= sh_in & shReg_in (regCount-1 downto 1);

end if;
end if;
end process;
-----------------------------------------------------------------

The other type does not include a sensitivity list. Instead, it employs one or more condition(s) that would postpone the execution of the process until it is met. Although this is not synthesizable, this is good for creating testbench codes. Shown below is a sample code.

-----------------------------------------------------------------
process --no sensitivity list
begin

wait until (clk'event and clk = '1')
if rst = '1' then

shReg _out <= (others => '0');

elsif clk'event and clk = '1' then
if shiftEn = '1' then

shReg _out <= sh_in & shReg_in (regCount-1 downto 1);

end if;
end if;
end process;
-----------------------------------------------------------------

Here, without the sensitivity list, I have to make rst synchronous which is I don't usually do. What will happen is that when rst is high, shReg_out will reset back to "00..." at the next clock cycle. This won't be detrimental to my output(s). I just have to make this synchronous with the clock in order for me to simulate its events.

References:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.
(2) Pellerin, D. and Taylor, D., VHDL Made Easy, Prentice Hall PTR, 1996.