VHDL Part 15 : Behavioral vs Structural Description

I think the knowledge of the difference between behavioral and structural description is very important for a vhdl coder. For my designs, I am fond of using structural coding for topblocks and behavioral for the subblocks. Some of my definitions here are based from my observation while others are form reference cited at the bottom of this post.

Behavioral description of a circuit is the highest level of abstraction in VHDL. Here, the circuit is described in terms of it operation with respect to time. All operations are in one level of code. The operations are described in a way that the designer of a sequential circuit infers a register. The code in VHDL Part 10 is an example of a behavioral code. The code is shown below.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shiftReg is
generic (regCount : natural := n); -- replace n with 4, 5, 8, etc. depends on the number you need
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
shiftEn : in STD_LOGIC;
sh_in : in STD_LOGIC;
shReg _in : in STD_LOGIC_VECTOR (regCount-1 downto 0);
shReg _out : out STD_LOGIC_VECTOR (regCount-1 downto 0));
end shiftReg;


architecture Behavioral of shiftReg is

begin

process (rst, clk)
begin

if rst = '1' then

shReg _out <= (others => '0');

elsif clk'event and clk = '1' then
if shiftEn = '1' then

shReg _out <= sh_in & shReg_in (regCount-1 downto 1);

end if;
end if;
end process;

end Behavioral;
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Structural description, on the other hand, is a circuit description in terms of its components. it can either create a low level description, much like a hierarchy in a block diagram. Whenever you see a component instantiated in a code, that code employs structural description of the circuit. The components are connected in the form of a netlist. This is for better manageability and reusability. Show below is the code for VHDL Part 6. The code below is a structural description of an n-bit register.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ckt_reg is
generic (pattern : natural := 4);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
loadEn : in STD_LOGIC;
reg _in : in STD_LOGIC_VECTOR (regCount-1 downto 0);
reg _out : out STD_LOGIC_VECTOR (regCount-1 downto 0));
end ckt_reg ;

architecture Behavioral of ckt_reg is

component dFF
port (clk, rst, loadEn, D_in : in std_logic;
D_out : out std_logic);
end component;

begin

iFF : for i in 0 to regCount-1 generate
FF : dFF port map (clk=>clk, rst=>rst, loadEn=>loadEn, D_in=>reg _in(i), D_out=>reg _out(i));
end generate iFF;

end Behavioral;
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Reference:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.