VHDL Part 20 : Seven Segment Decoder

I had shown below the code that I use for seven segment display (SSD) decoder. I need to use this so that I can display the outputs of previous post on a sevent-segment LED.

Please note that the output SSD_out can change depending on the seven segment display you are using.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SSD is
generic (sInWidth : natural := 4;
sOutWidth : natural := 7);
port(SSD_in : in std_logic_vector (sInWidth-1 downto 0);
SSD_out : out std_logic_vector(sOutWidth-1 downto 0) );
end SSD;

architecture Behavioral of SSD is
begin
process (SSD_in)
begin

case SSD_in is
-- change SSD_out based on the configuration of the seven-segment you are using
-- kindly check the specs
when "0010" => SSD_out <= "0010010"; -- 2
when "0011" => SSD_out <= "0000110";
when "0100" => SSD_out <= "1001100";
when "0101" => SSD_out <= "0100100";
when "0110" => SSD_out <= "0100000";
when "0111" => SSD_out <= "0001111";
when "1000" => SSD_out <= "0000000";
when "1001" => SSD_out <= "0001100"; -- 9
when "1010" => SSD_out <= "0001000";-- A
when "1011" => SSD_out <= "1100000";
when "1100" => SSD_out <= "0110001"; -- C
when others => SSD_out <= "1111110"; -- '-'
end case;
end process;
end Behavioral;
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Reference:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.