VHDL Part 14 : 2-digit Counter

My previous post showed one of the codes for a 1-digit counter. I had shown below the code for a 2-digit counter. For this, I will be needing two variables. One for the ones place, the other for the tens. This will emulate a 60-second counter. I cited the reference below.

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity upCounter2 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
countEn : in STD_LOGIC;-- enable
count_in : in STD_LOGIC;
count_out1 : out INTEGER RANGE 0 To 6; -- ones
count_out2 : out INTEGER RANGE 0 To 9); -- tens
end upCounter2;


architecture Behavioral of upCounter2 is

begin

process (rst, clk)

variable count_v1 : integer range 0 to 10; -- ones
variable count_v2 : integer range 0 to 6; -- tens

begin

-- async reset
if rst = '1' then

-- initialize the outputs and the variables to 0
count _out1 := 0;
count_v1 := 0;
count _out2 := 0;
count_v2 := 0;

elsif clk'event and clk = '1' then
if countEn = '1' then

count_v1 := count_v1 + 1;

if count_v1 = 10 then

count_v1 := 0;
count_v2 := count_v2 + 1;

if count_v2 = 6 then

count_v2 := 0;

end if;
end if;
end if;
end if;

count_out1 <= count_v1;
count_out2 <= count_v2;

end process;
end Behavioral;
-----------------------------------------------------------------

References:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.