VHDL Part 27 : Comparator using if-then-else

The circuit code I had shown below compares two inputs. I have four outputs. The appropriate output gives a high signal whenever the corresponding condition is satisfied. I need this for matching.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity compare1 is
generic (compWidth : natural := 8);
port(
clk : in std_logic;
rst : in std_logic;
comp_in1 : in std_logic_vector (compWidth-1 downto 0);
comp_in2 : in std_logic_vector (compWidth-1 downto 0);
comp_out1 : out std_logic;
comp_out2 : out std_logic;
comp_out3 : out std_logic;
comp_out4 : out std_logic;
);
end compare1;

architecture Behavioral of compare1 is
begin
process (clk, rst)
begin

if rst = '1' then

comp_out1 <= '0';
comp_out2 <= '0';
comp_out3 <= '0';
comp_out4 <= '0';

elsif clk'event and clk = '1' then

if comp_in1 = comp_in2 then

comp_out1 <= '1';
comp_out2 <= '0';
comp_out3 <= '0';
comp_out4 <= '0';

elsif comp_in1<
comp_in2 then

comp_out1 <= '0';
comp_out2 <= '1';
comp_out3 <= '0';
comp_out4 <= '0';

elsif comp_in1 > comp_in2 then

comp_out1 <= '0';
comp_out2 <= '0';
comp_out3 <= '1';
comp_out4 <= '0';

elsif comp_in1 /= comp_in2 then -- not equal

comp_out1 <= '0';
comp_out2 <= '0';
comp_out3 <= '0';
comp_out4 <= '1';

end if;
end if;
end process;
end Behavioral;
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The circuit above could be easily implemented using when-else statement. However, I want the outputs to be synchronized with the clock.

References:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.