VHDL Part 30 : Multiplexer

I need multiplexer too for the current ____ generator I'm working on so I must learn it. A multiplexer, commonly known as MUX, is used when out of several inputs, there can only be one output. To choose the between inputs, a selector is needed. In implementing a MUX in vhdl, care must be taken in order not to generate unintended gates. You may check the results, especially the warnings generated after synthesizing your design (by double clicking Synthesize-XST in the Processes subwindow).

A sample code is
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux1 is
generic (muxLen : natural := 4);
port(
mux_in1 : in std_logic_vector (muxLen-1 downto 0);
mux_in2 : in std_logic_vector (muxLen-1 downto 0);
mux_in3 : in std_logic_vector (muxLen-1 downto 0);
mux_in4 : in std_logic_vector (muxLen-1 downto 0);
mux_sel : in std_logic_vector (1 downto 0);
mux_out1 : out std_logic_vector(muxLen-1 downto 0);
mux_out2 : out std_logic_vector(muxLen-1 downto 0)
);
end mux1;

architecture Behavioral of mux1 is
begin

mux_process : process (mux_sel)
begin

case mux_sel is

when "00" => mux_out1 <= mux_in1; mux_out2 <= "0011";
when "01" => mux_out1 <= mux_in2; mux_out2 <= "0010";
when "10" => mux_out1 <= mux_in3;
when "11" => mux_out1 <= mux_in4;
when others =>

end case;
end process mux_process;
end Behavioral;
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The code above did not generate errors but there are 2 warnings which will be discussed on the next post. Shown below is the result of my simulation.


References:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.
(2) Xilinx MUX Toolbox