VHDL Part 6 : n-bit register using D-flipflop

I thought maybe I can use the d-flipflop I had done before to generate an n-bit register. Guided by my usual references, I found out I can use the for-generate statement to do this. After trying to code it, I simulated and I succeeded.

Here, I had posted another way of implementing an n-bit register in vhdl. I had implemented a 4-bit register again but this time I did it by cascading 4 D-type flipflops I had posted in VHDL Part 4 using the for-generate construct.

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ckt_reg is
generic (regCount : natural := 4);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
loadEn : in STD_LOGIC;
reg _in : in STD_LOGIC_VECTOR (regCount-1 downto 0);
reg _out : out STD_LOGIC_VECTOR (regCount-1 downto 0));
end ckt_reg ;

architecture Behavioral of ckt_reg is

component dFF
port (clk, rst, loadEn, D_in : in std_logic;
D_out : out std_logic);
end component;

begin

iFF : for i in 0 to regCount-1 generate
FF : dFF port map (clk=>clk, rst=>rst, loadEn=>loadEn, D_in=>reg _in(i), D_out=>reg _out(i));
end generate iFF;

end Behavioral;
------------------------------------------------------------------

I had used the dFF. For me to call this circuit into ckt_reg, on the Sources subwindow, highlight the topblock ckt_reg then on the Processes subwindow, Add Existing Source. Locate the file dFF.vhd. Double click them to open it in the current source ckt_reg. Or on the Sources subwindow, right click the topblock and select Add Source...Then locate the file and double click it.

For-generate is a concurrent construct which allows the section enclosed to be repeated a number of times. Here, I have created 4 instances of D-flipflops.

Reference:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.

VHDL Part 5: n-bit Register

Today, I tried implementing an-bit register in vhdl that functions much the same way as d-flipflop but the number of bits for data ports I had increased from 1 to n. I replace std_logic with std_logic_vector. My references are listed at the bottom of this post.

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ckt_reg is
generic (pattern : natural := 4);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
loadEn : in STD_LOGIC;
reg _in : in STD_LOGIC_VECTOR (regCount-1 downto 0);
reg _out : out STD_LOGIC_VECTOR (regCount-1 downto 0));
end ckt_reg ;

architecture Behavioral of ckt_reg is
begin

process (clk, rst)
begin

if rst = '1' then

reg _out <= '0';

elsif clk'event and clk = '1' then
if loadEn = '1' then

reg _out <= reg_in;

end if;
end if;
end process;

end Behavioral;
------------------------------------------------------------------

generic (regCount : natural := 4);
-- generic is a way to specify a static parameter. It is good for flexibility and reusability. For the code above n is 4. To change the port size, do the editing in the generic statement.
Syntax is

generic (generic_name : generic_type := generic_value);

Generic types can be any predefined numeric subtypes like integer, natural, positive, etc.

reg _in : in STD_LOGIC_VECTOR (regCount-1 downto 0);
-- reg_in is declared as a 4-bit vector with the leftmost bit as the MSB. if you want the rightmost bit to be the MSB, use: (0 to regCount-1).

Simulation Results
Here's my simulation results. The is set at 3000 ns.

References:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.
(2) Pellerin, D. and Taylor, D., VHDL Made Easy, Prentice Hall PTR, 1996.