Digital signal processing has the reputation of being hard to understand. Much more when you put it in a hardware language. Learning the foundations and how to convey the language of field programmable gate array-based digital signal processing is like a military man in a battlefield. I am in a notoriously chaotic place, fighting my way to safety and have no time to carefully take note of events. Further, if I flip through typical books on DSP, it seems like I need a brain well-grounded in mathematics, where analytical skills are rife before I plunge into the field. My goal here is to patiently (as much as I can) take down notes on whatever I learn to move forward in this journey.
Oh, the difficulty of understanding mathematical subtleties and knowing what they mean from a practical viewpoint.
Learning accelerated computing and digital signal processing from the very beginning.
Google Search
something to ponder
“...it is impossible to explain honestly the beauties of the laws of nature in a way that people can feel, without their having some deep understanding of mathematics. I am sorry, but this seems to be the case."
- R Feynman
- R Feynman
Blog Archive
Topics
- accessing the serial port in FPGA (1)
- accumulator (1)
- aggregate assignment (1)
- Albert Einstein (1)
- behavioral description (1)
- best FPGA book (1)
- case statement (2)
- comparator (2)
- components (1)
- computer science conference (1)
- counter (3)
- Counter with Seven-Segment Display (1)
- critical path (1)
- d flipflop (2)
- data type conversion (1)
- debouncer (1)
- decoder (1)
- ERROR:HDLParsers:1401 (1)
- ERROR:HDLParsers:3562 (1)
- ERROR:HDLParsers:3566 (1)
- exit loop (1)
- finite state machine (4)
- flipflop (1)
- for-generate (1)
- FPGA (1)
- fpga-based 3D graphics system (1)
- generic maps based on input signal (1)
- globally static expression (1)
- illusion (1)
- initializing signals (1)
- integer (1)
- integer to std_logic_vector converter (1)
- log file (3)
- Marilyn Monroe (1)
- mask generator (8)
- maximum combinational path delay (1)
- Maximum output required time before clock (1)
- minimum input arrival time before clock (1)
- minimum period (1)
- multiplexer (2)
- n-bit Register (2)
- natural (1)
- next loop (1)
- port map (1)
- positive (1)
- priority encoder (1)
- reconfigurable computing (1)
- sensitivity list (1)
- serial in serial out shift register (1)
- serial in serial out shift-left register (1)
- serial in serial out shift-right register (1)
- Seven Segment Decoder (1)
- shift register (1)
- shift register using for-loop (1)
- shift-left register (1)
- shift-left register using for-loop (1)
- shift-right register (1)
- shift-right register using for-loop (1)
- signal (1)
- signal vs variable (1)
- structural description (1)
- synthesis report (1)
- techware documentation (1)
- timing summary (1)
- two-digit counter (1)
- variable (1)
- vhdl (9)
- vhdl arrays (1)
- vhdl boolean (1)
- vhdl code for UART (1)
- vhdl code structure (1)
- vhdl counter (1)
- vhdl data types (1)
- vhdl entity (1)
- vhdl for loop (1)
- vhdl library (1)
- vhdl loops (1)
- vhdl packages (2)
- vhdl process (1)
- vhdl subtypes (1)
- vhdl tutorial (1)
- vhdl while loop (1)
- wait statement (1)
- WARNING:Xst:1294 (1)
- WARNING:Xst:1710 (1)
- WARNING:Xst:1895 (1)
- WARNING:Xst:737 (2)
- WARNING:Xst:819 (1)
- when-else (1)
- willpower (1)
- writing documentation (1)
- xilinx timing summary (3)
- Xilinx tutorial (1)
About Me
- tahder
- I am fearfully and wonderfully made..
Posts
No comments:
Post a Comment