Thursday, July 24, 2008

VHDL Part 3 : Xilinx ISE tutorial

(Note: Click on a picture for clearer view.)

Xilinx has its own tutorials on different tools. Given that Xilinx ISE is already installed (I am using version 9.2i though 10.1 is already available as of this writing), on the Menu click on Help, then Tutorials and choices are listed. What I give here is just a very quick way to get started with Xilinx. I will begin with a very simple circuit shown below.

(1) Open Xilinx ISE Project Navigator by double clicking its icon on your desktop or go to
Start > Programs > Xilinx ISE #.#i > Project Navigator.
Please note that #.#i is the version that is installed. You may also type ise from the run command.

(2) To create a new file, in the project navigator menu, select File then New Project. The New Project Wizard appears.

Enter the project name ckt_1 on the Project Name text box. If you want to change the directory of the project, click on the browse button (with three dots) and select the folder and subfolders you wish to save your project in. For this example, the top level source type is still HDL.

Click Next.

(3) The Device Properties window opens in which you can change the device that you will use. Should there be no device preference for the moment, you may copy my settings below.

Family : Spartan3E
Device : XC3S500E
Package : FG320
Speed : -4
Synthesis Tool : XST (VHDL/Verilog)
Simulator : ISE Simulator (VHDL/Verilog)
Preferred Language : VHDL
Enable Enhanced Design Summary : tick the check box

Click Next.

(4) The Create New Source window appears.

Click New Source button on the right hand side of the window.

The Select Source Type window appears on top.

Select VHDL Module. Type ckt_1 on the File name text box. This will be the source. The Project name you have entered earlier is the folder in which all files for this project will be saved.

Click Next.

(5) The Define Module windows appears. Enter the following settings.

Port Name / Direction
ckt_in1 / in
ckt_in2 / in
ckt_in3 / in
ckt_out / out

Click Next.

(6) A Summary window of what you had entered appears. If everything in it are right, click Finish. If not, click the Back button and make the necessary changes.

(7) A popup window asking you if you would like to create the directory. Click Yes.

(8) A window for removing the source and creating a new one then appears. Just click Next.

(9) The Add Existing Sources then appears. Here, you can add sources which you have already made from other folders or which you have pasted to this folder (ckt_1). For now, just click Next.

(10) The Project Summary window appears. Click Finish if everything there is right. If not, click the Back button.

(11) In the workspace, the Design Summary might appear first. On the bottom of it click on the ckt_1.vhd tab. You can see the unfinished code. Those words with colors are reserved words. Do not use them in naming ports, signals, variables or any user-created name.
The -- is for comments. Any word(s) written after -- is ignored when the program runs. Complete the code as shown below. Please note that I added the ports clk and rst and the statements after begin. So even if you forgot to include ports on Step 5, you may still add them at this stage.

library IEEE;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ckt_1 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ckt_in1 : in STD_LOGIC;
ckt_in2 : in STD_LOGIC;
ckt_in3 : in STD_LOGIC;
ckt_out : out STD_LOGIC);
end ckt_1;

architecture Behavioral of ckt_1 is

(rst, clk)

if rst = '1' then

ckt_out <= '0';

clk'event and clk = '1' then

ckt_out <= (ckt_in1 and ckt_in2) or (not ckt_in3); end if;
end process;

end Behavioral;

I had enclosed some parts of the equation in parenthesis for readability. Do not forget to save your work.

This code means that when reset 'rst' is high, the output is low. When reset is low (implicitly defined) and upon the rising edge of the clock, the program must perform the statement
(ckt_in1 and ckt_in2) or (not ckt_in3)
and put the answer on the output port 'ckt_out'. Obviously, the gates on the circuit shown above (before Step 1) is just replaced by the words 'and ', 'or ' and 'not'.

(12) Next thing to do is to check the syntax. On the left hand side of the window is the Processes subwindow (just below the Sources window). Click on the + sign beside Synthesize - XST to expand it. Double click on Check Syntax.

See the Transcript subwindow (at the bottom) if the check syntax is completed successfully. If the syntax check is successful, it will show a green check mark beside 'Check Syntax'. If not, you will see a red 'x' mark beside Check Syntax and will indicate on the Transcript subwindow that the Process "Check syntax" failed. You will also see the error there.
Example is shown below where I changed ckt_in1 to ckt in line 41 to produce an error.

The error on the Transcript subwindow is shown in blue underlined letters. The line number is also included; however, if you have a long code and want to go to the error immediately, you may right click on the error and select Go to Source and it will go to the specified line. If you want to search the Xilinx database for some help re the error right click on the error and select Go to Answer Record and a new tab will open on the command window.

(13) If the Process "Check Syntax" is completed successfully, double click on View RTL Schematic. This is to check if there are still errors or warnings which are not seen by the Check Syntax Process. Errors are indicated by red 'x' marks while warnings are identified by yellow exclamation marks. Some warnings are ok, some must be debugged.
Shown below is a successful generation of the RTL schematic. This opened on the Command subwindow.

To go deeper the schematic one level, double click anywhere within the green block. To go up one level, double click anywhere outside the green block(s). Close the ckt_1.ngr tab.

(14) Now, we simulate the circuit using the built-in simulator of ISE. On the Sources subwindow (upper left), click on the Sources for: list box. Choose Behavioral Simulation.

Select ckt_1. Then on the Processes subwindow, double click on Create New Source. The New Source Wizard - Select Source Type window will pop out. Click on Test Bench WaveForm, then type ckt_tb1 on the Filename text box. Click Next.

(15) The New Source Wizard - Associate Source window appears. The circuit/source to which you want to associate the testbench must be highlighted. This is important especially if you have several blocks in one file and you want to simulate just a subblock. Click Next.

(16) The New Source Wizard - Summary window appears. If everything is correct, click Finish. If not click on the Back button.

(17) The Initial Timing and Clock Wizard window appears. Settle on the defaults for now. Click Finish.

(18) The Testbench waveform appears on the Command window. The end of it seems very limiting. Right click on this subwindow, choose Set End of TestBench... then type 2000 on the Test Bench Ends: text box. Then click OK.

(19) If you want to put 'rst' after 'clk', click and drag it then drop it below 'clk'. I had set the waveforms as shown below. Do this by clicking on the light blue lines or between two [light blue] lines.

Save your work.

(20) To simulate the circuit using the testbench we have created, on the Processes subwindow, select the Processes tab. Expand the Xilinx ISE Simulator by clicking on the + sign beside it. Double click on Simulate Behavioral Model.

(21) The Simulation results will appear on the Command subwindow. At first, it may show only the first 1000ns of the simulation. To set the whole 2000ns of it, on the upper part of the ISE window, on the text box below the menu type 2000 and click the Run for a Specified Time icon just beside the text box and press F6 or click on Zoom to Full View icon (above the text box, beside the Zoom Out icon).

(22) Shown below is my simulation result. The port 'rst' is asynchronous, meaning it is independent of the clock 'clk'. At the time when reset is high, the output 'ckt_out' is low. For every rising edge of the clock, the operation is done and produces the appropriate value of the output on 'ckt_out'. You can see that for every clock cycle, the correct output is produced.

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