VHDL Part 29 : Priority Encoder

I needed a decoder. Since there are a variety of ways to do it, I needed to know which one is best. By 'best' I mean the one that generates lesser number of logic gates at the fastest speed possible. i had learned though, that there is a trade-off between speed and area. The operation of an encoder is inverse to that of a decoder. An encoder has (2**n) input bits and n output bits. The functionality of an encoder is such that only one bit in the input must have a '1' and the rest, '0'. Problem is, if I have other bits in the input which has a value of '1'. A way I get around this is by assigning a priority to each of the input bits. This way, the code cares only about the highest priority (as seen on the index value) and not on other bits in the input. Shown below is a sample code.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity encode1 is
port(
enc_in : in std_logic_vector (3 downto 0);
enc_out : out std_logic_vector(1 downto 0)
);
end encode1;

architecture Behavioral of encode1 is
begin

enc_out <= "11" when enc_in(3) = '1' else
"10" when enc_in(2) = '1' else
"01" when enc_in(1) = '1' else
"00";

end Behavioral;
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Simulation

Shown below is my simulation result. As can be seen, when all bits of my input has a value of '1', since my MSB of the input has the highest priority, the first line of code in the architecture body was executed.


References:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.
(2) Xilinx Priority Encoder Toolbox