Wednesday, September 3, 2008

VHDL Part 33 : ERROR:HDLParsers:3562

Before I proceed with FSM, let me share this.

I was using Xilinx ISE 9.1 before and had encountered this error

ERROR:HDLParsers:3562 - project_name line_# Expecting 'vhdl' or 'verilog' keyword, found 'work'.

I was already getting bugged with this error because I don't understand what it wants to convey. Until I landed on this site.

There are a couple or more ways the kind people there suggested on how to get rid of that error. I tried the easiest one which is to store the project in a directory path that has no spaces. I was saving my projects in My Documents folder. So I transferred all my projects under Xilinx ISE folder and there. The error disappeared. I find this bug is kind of funny too. I then switched to version 10.1.

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