VHDL Part 40 : Declaring Components in Packages

If I use a code as a component, I can then use it in another circuit which allows me to create designs in hierarchy. I find this good since it enables code reusability. However, I find it tiring to declare codes/components again and again everytime I revise my topblock. I sometimes place these components in a library so that I can do away with explicitly writing such codes.

For instance I need to instantiate a shift register, 4-bit  register, a decoder and an encoder. So first I have to create individual codes for each of these 4 circuits. You may see my previous posts for their sample codes. 

4-bit register -- VHDL Part 5

shift register -- VHDL Part 10

encoder -- VHDL Part 29

decoder -- VHDL Part 26

What I will write here now is the way I package my components and then proceed to the topblock. I will not make use of generics here.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

package component1 is

-- *********************

-- here's the 4-bit register

-- *********************

component ckt_reg is

Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
loadEn : in STD_LOGIC;
reg _in : in STD_LOGIC_VECTOR (regCount-1 downto 0);
reg _out : out STD_LOGIC_VECTOR (regCount-1 downto 0));
end component;

-- **************************

-- here's the 4-bit shift register

-- **************************

component shiftReg is

Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
shiftEn : in STD_LOGIC;
sh_in : in STD_LOGIC;
shReg _in : in STD_LOGIC_VECTOR (3 downto 0);
shReg _out : out STD_LOGIC_VECTOR (3 downto 0));
end component;

-- *****************

-- here's the encoder

-- *****************

component encode1 is

Port ( enc_in : in std_logic_vector (3 downto 0);
enc_out : out std_logic_vector(1 downto 0));
end component;

-- *****************

-- here's the decoder

-- *****************

component decode1 is

Port ( clk : in std_logic;
rst : in std_logic;
dec_in : in std_logic_vector (1 downto 0);
dec_out : out std_logic_vector(7 downto 0));
end component;

end component1;

----------------------------------------------------------------------------------------------------------

-- *******************************

-- here's my topblock

-- *******************************

----------------------------------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

use work.component1.ALL;

entity top1 is
port(
clk : in std_logic;
rst : in std_logic;

en : in std_logic;

top_sh : in std_logic; -- for shift register
top_in : in std_logic_vector (1 downto 0);
top_out : out std_logic_vector(decWidth-1 downto 0)
);

end top1;

architecture struct of top1 is

signal tmpReg2Sh, tmpSh2Enc :  std_logic_vector (3 downto 0);

signal tmpEnc2Dec :  std_logic_vector (1 downto 0); 

begin

-- I will use positional mapping here

COMP1 : ckt_reg port map (clk, rst, en, top_in, tmpReg2Sh);

COMP2 : shiftReg port map (clk, rst, en, top_sh, tmpReg2Sh, tmpSh2Enc);

COMP3 : encode1 port map (tmpSh2Enc, tmpEnc2Dec);

COMP4 : decode1 port map (clk, rst, tmpEnc2Dec, top_out);

end struct;

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Here's the catch: I was not able to simulate this due to my tight schedule. But if there are any errors, I expect them to be minor.

References:

(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.
(2) Xilinx Toolbox