VHDL Part 44 : Mask Generator 3

I tried his code and added some lines so that I could tap a row for the output. However, I could not view the RTL schematic so I posted a follow up question.

Hi jeppe

Thank you so much for helping me. 


I had added some lines of code so that I could access a row for the output.

for j in 0 to r-1 loop
for i in 0 to n-1 loop
if maskIn_P(i) = maskIn_R(j) then
memory(i)(j) <= '1'; --THIS IS LINE 68
else
memory(i)(j) <= '0'; end if; end loop; end loop; elsif readEn = '1' then maskOut <= memory(conv_integer(address)); else maskOut <= "ZZZZZ"; end if; end if; end process; 

Here's my port declaration:

address : in STD_LOGIC_VECTOR (r-1 downto 0);
patternIn : in STD_LOGIC_VECTOR (n-1 downto 0);
referenceIn : in STD_LOGIC_VECTOR (r-1 downto 0);
maskOut : out STD_LOGIC_VECTOR (n-1 downto 0));


I got no error in checking the syntax but got one when I tried to view the RTL schematic. 
line 68: Index value <8> is not in Range of array <0>>.

I'm not sure but I have a feeling that the error is caused by this line
maskOut <= memory(conv_integer(address));

Is it necessary for n and r to be equal? I had tried letting n be equal to 8 and r to 32
but it won't synthesize. When I tried using your values which is 10 for both, it did 
synthesize. So long as n and r are equal it synthesized. But I can't have have equal values for n and r 
since my reference vector must be much longer than my pattern vector.

Thanks again,
tahder