Sunday, September 14, 2008

VHDLPart 42 : Mask Generator 1

Let me share the conversation that I had with jeppe from the vhdl forum in VelocityReviews. This is the question I posted (taht was March 2008).

Hello everyone,
I am new to vhdl and I want to implement a synthesizable mask generator. 
I thought about implementing it with a 2D array (like a ROM) that is usually seen in vhdl books.
My problem is that I'm stuck with generating the contents inside the array since an index will output a '1' only if an n-bit element is equal to another n-bit element. I don't want to have a build up of equality comparators. Is it possible to have only one comparator for the whole system? or a single row of comparators that will work for all the rows in the memory? I tried doing this:

architecture bhv of maskGen is

subtype patternArray is std_logic_vector (n-1 downto 0);
type referenceArray is array (r-1 downto 0) of patternArray;
signal memory : referenceArray;

-- this is for the magnitude comparator
component magComp
port (A, B : in std_logic_vector (n-1 downto 0);
EQ : out std_logic);
end component;

-- The behavioral architecture for magComp is only:
-- EQ <= '1' when A=B else '0'; begin process (rst, clk, maskEn) begin if clk = '1' and clk'event then if maskEn = '1' then for j in 0 to r-1 loop for i in 0 to n-1 generate -- this is line 69 magComp port map (A=>maskIn_P(i), B=>maskIn_R(j), EQ => memory(i)(j));
end generate;
end loop;
end if;
end if;

end process;
end bhv;

However, this gave me an error:
Line 69. parse error, unexpected GENERATE, expecting LOOP.

Can anyone explain why the code generated such an error? 

I really do not want to implement the code above since it might result to horrendous amount of logic.
What do I do now? 


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