VHDL Part 39 : Packages in VHDL

I am now studying how to create packages in VHDL. Packages contain common design modules that I can use in VHDL source codes. By 'common design modules', I am referring to components, functions and procedures. Components I know so I will start on this. Structural programming has done me good in my  past VHDL designs since it gives me a much cleaner look and modularity. But it can be very exhausting for me especially whenever I am instantiating several components again and again. This often happens to me since I do not delete my code revisions. I can do copy-paste in component declarations; however, I want to try package and see which eases my tasks better. See you in my next post for a sample code on this trial of mine!