VHDL Part 36 : Finite State Machine Sample Design Illustration

So I want to design and simulate a state machine using VHDL. First, since I am a starter, I must have an illustration of want I want my circuit to go through. I have made a very simple flow as illustrated below.

And here's what I want to happen at each state.

I then need I/O ports of course. For my inputs, I'll have clk (master clock), rst (master reset) and cond_1 and cond_2 as conditions. My outputs will be the enables of my 4 blocks.