VHDL Part 41 : Arrays

I happen to take interest in vhdl arrays when I was trying to come up with a code for mask generator. A mask generator is like a multplication table where you have values along x and along y and to get a '1', certain values for x and y must be satisfied. I was trying to come up with a design that won't build a tremendous amount of logic so I tried to check out arrays.

Arrays in VHDL can be 1D, 2D or 1Dx1D.

Here is a scalar : 0

Here is a 1D : 

11001

Here is a 1Dx1D :

11001

10100

00101

11100

Here is a 2D :

1 1 0 0 1

1 0 1 0 0

0 0 1 0 1

1 1 1 0 0

I just have a problem with these. According to the book Circuit Design with VHDL, they are generally not synthesizable. 

Reference:

(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.