VHDL Part 21 : Counter with Seven-Segment Display

This time I had learned to connect the counter on VHDL Part 19 and the Seven-Segment Display driver on VHDL Part 20.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter_SSD is
generic (cOutWidth : natural := 4;
sOutWidth : natural := 7);
port (clk : in STD_LOGIC;
rst : in STD_LOGIC;
set : in STD_LOGIC;
dispEn : in STD_LOGIC;
disp_out : in STD_LOGIC_VECTOR (sOutWidth-1 downto 0));
end counter_SSD;

architecture Behavioral of counter_SSD is

component counter3
-- note the declaration of generic statement in component instantiation
generic (cOutWidth : positive);
port (clk : in STD_LOGIC;
rst : in STD_LOGIC;
set : in STD_LOGIC;
countEn : in STD_LOGIC;
count_out : in STD_LOGIC_VECTOR (coutWidth-1 downto 0));
end counter3;

component SSD
-- note the declaration of generic statement in component instantiation
generic (cOutWidth : positive;
cOutWidth : positive);
port (SSD_in : in std_logic_vector (sInWidth-1 downto 0);
SSD_out : out std_logic_vector(sOutWidth-1 downto 0) );
end SSD;

-- this is for the internal connection of the two components
-- note that we are trying to connect the output port of counter3 to the input port of SSD
signal count_s : std_logic_vector (cOutWidth-1 downto 0);

begin

counter : counter3
-- map the generic statement of counter3 to the generic statement of the topblock
-- note the mapping operator => which is very much different to the assignment operator =>
-- it is fine that to map a generic with a generic that has the same name
generic map (cOutWidth => cOutWidth);

-- likewise, it is fine that to map a port with a port that has the same name
-- note that commas separate the port maps
port map (clk=>clk,
rst=>rst,
set=>set,
countEn=>dispEn,
count_out=>count_s);

display : SSD

generic map (sInWidth =>cOutWidth,
sOutWidth=>sOutWidth);

port map (SSD_in=>count_s,
SSD_out=>disp_out);

end Behavioral;
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I had labeled each of the two components. This is very useful in my simulations so that when an error or a warning is generated, the component that causes that error or warning is easily identified by the simulator. It will then be easy for me to debug it.

The simulator will look for the source codes of the two components that were instantiated. See VHDL Part 6 for a post on how to add the source codes into the project.