Timing Summary: Maximum output required time after clock

The remaining timing path domain is the Maximum output required time after clock. According to Xilinx toolbox, it is the maximum path from inputs to outputs. Gabor from Xilinx forums has a concise explanation on this.

---

Quote:

..."Maximum output required time after clock" refers to the delay from the clock to external outputs of the top-level design for the worst case pins.

---

Check this forum for more details.

Timing Summary: Minimum input arrival time before clock

The second domain in the Timing Summary (Design Summary, Synthesis Report) is the Minimum input arrival time before clock. Based on Xilinx toolbox, it is the maximum path from the sequential elements to all primary outputs. Again, Gabor has a very good explanation on this one.

---

Quote:

"Minimum input arrival before clock" is the required setup time from the worst case top-level design input to the clock...Again after synthesis these are only estimates, you need to place and route the design to get hard numbers.  Also if your design as synthesized represents only a portion of a larger design, the input and output timings may be significantly different, as they may not represent signals going on or off of the FPGA.

---

He also stressed that if the time indicated in "Minimum input arrival before clock" is less than the time in the "Minimum Period", it may be possible to run the design at the maximum clock frequency specified.

Click here to get to the source.

Timing Summary: Minimum Period

The first item in the list is the Minimum period, one of the domains of timing paths. According to Xilinx toolbox, it is the maximum path from all primary inputs to the sequential elements. One good explanation is given by, again, gszakacs in a Xilinx forum.

---

Quote:

Minimum period" after synthesis is an estimate of the clock period for signals inside the design.  Thus you can invert this to get a feel for maximum clock frequency.  This is not a hard actual number, as you can only see the true numbers after place&route.  Also this may not be the actual minimum period for the design if you are limited by input and output timing.  It only calculates the worst case path timing from clock edge to clock edge for flip-flops within the design.  So if you have a path consisting of external input to flip-flop through look-up table to another flip-flop to an external output, only the path from the first flip-flop through the look-up table to the second flip-flop is measured for "Minimum period".

---

He also added

---

Quote:

The minimum clock period depends on paths that go from the Q output of a flip-flip to the D input of another flip-flop in the design...The worst case path may in fact not be connected at the top level.  You would need to look at a static timing report to see what the path is and whether you use it...Also note that the timing reported by synthesis is a best-guess estimate of the achievable timing after place and route.  This is usually only useful when designing reusable IP for example or some other subsystem you would like to know the possible best case speed of.   The real timing performance of a design is only known after place & route and can be found in the post P&R static timing report.  Using the advanced properties for static timing report generation you can get a verbose report that includes uncovered paths in case there are critical paths that have not been constrained.

---

You may want to visit that forum.

Maximum combinational path delay: No path found

In the Design Summary, under Synthesis Report (Timing Summary heading), I always see this list:

Minimum period:

Minimum input arrival time before clock:

Maximum output required time after clock:

Maximum combinational path delay:

The last item interests me most (among the four) since it sometimes gives me this: 

Maximum combinational path delay: No path found.

I do not know whether this is good. So I checked. In a Xilinx forum, expert contributor gszakacks said,

---

Quote:

This is normal if there is no path from a top-level input to a top-level output that is not clocked. I assume your design is fully pipelined, thus no combinatorial paths from input to output?

---

According to a Xilinx ModelSim Simulation Tutorial from Computer and Information Science, University of Pennsylvania, 

---

Quote:

Maximum combinational path delay...is the maximum delay for signal propagation in your design, so changing signals faster than [this] will result in unexpected behavior.

---

They have an example there (Timing Simulation: Combinational Logic Section 2), where they made the signal transition faster which resulted in simulation failure - the output signals do not match the input signals because the inputs change too fast.

Critical Path

I heard of 'critical path' for the first time yesterday during a meeting. Our project leader was asking about an incorrect output in the main block. My teammate explained about a part in his design that is asynchronous. Then the proj leader mentioned 'critical path'. I do not know what it is so I did some reading. According to Design Recipes for FPGAs, during analysis of static timing, the delay from each input to each output of all devices is computed. The delays are then added up along each path through the circuit to get the critical path through the design. The fastest design speed is therefore obtained. The critical path is an approach to logic optimization.

Reference:

(1) Wilson, P., Design Recipes for FPGAs, 2007, pp. 40 and187, Elsevier.

Writing techware documentation

I feel so terribly burdened by having to do documentation. I had already spent 4 days with it (still counting) and I'm so slow in doing it. I know this is important in reconfigurable computing advocacy but my problem is, I'm not so good with words. I especially hate highfalutin techie words that only geeks will understand but not the common people. There. That's my problem. How do I relay such a beautiful thing as accelerated computing to young people without them being terrified that this is something they might not be able to grasp? I don't know how to start with this so I need at least a reference. I want a book that will give me just what I need. I don't want to spend too much time in writing. I want to practice coding. So I checked amazon for a guide to writing with good reviews. I saw "Writing for Computer Science" by Justin Zobel has excellent reviews (5 reviews only :)).

I'm excited to quickly read this one since it only has less than 200 pages. There's a relatively high probability I'll be able to finish this tomorrow. Hope this could speed me up and help me finish writing within this week.

Addendum (Oct. 03, 2008): 

The book is very good! I just have to finish documenting one block. Hopefully, I'll be able to go back to coding this weekend!

VHDL Code for UART (transmitter only)

I used UART to check my outputs bit-by-bit for the previous project that I did. Unfortunately, since I needed only a transmitter, the VHDL code that I have is only for the TX. I would like to settle first the answer to my question, "What is UART?" I found a very clear and simple discussion from the site of Rose-Hulman Institute of Technology. UART stands for Universal Asynchronous Receiver Transmitter. It is a parallel to serial data transmitter and a serial to parallel data receiver. The 'Asynchronous' term is there because of the fact that the clock for the UART need not be synchronized to either transmit or receive system clocks. I needed this UART to send my data outputs to my CPU's buffer and have MATLAB® check those bits. My input ports are clock, reset, my input data (from 1 to n depending on the number of outputs that I need to read, remember number of outputs not the number of bits) and of course, my output which is just a std_logic type. The simple technique my teammate taught me is to use a counter that is triggered by a synchronous enable. For example, I need to read 4 outputs from my main block. This 4 bit vectors will be fed to the input of my UART. Those 4-bit vectors are, say, 8 bits each. The first count of the counter (my UART) will be for the start bit, the next 8 contains the data, the last bit, the tenth bit will be the stop bit. The start and stop bits are necessary for every UART. This repeats for all my data. For every count, these bits will be fed to the 1-bit output. I show below a sample portion, taken from the middle of my code.

when 111=>output<='0';--this is the start bit

when  112=> output <=input10(0);

when  113=> output <=input10(1);

when  114=> output <=input10(2);

when  115=> output <=input10(3);

when  116=> output <=input10(4);

when  117=> output <=input10(5);

when  118=> output <=input10(6);

when  119=> output <=input10(7);

when  120=> output <='1';--this is the stop bit

For instance, my count ended at 120. After closing my case statement I added an if-end if statement that just says if the counter is less than 200 then increment the counter. I was adviced to have larger number for my counter. Notice that I used 200 instead of 120 as my upper limit. 

Best FPGA introductory book

Like all FPGA starters, I also struggled for a book that will serve as an FPGA tutorial. It was only this year (copyright of this book is February 2008) that I found one. This is for me (so far) the best introductory FPGA book--FPGA Prototyping by VHDL Examples, authored by Pong Chu. Learning by doing is the most effective pedagogical style and this book did not fail to deliver that one. I find Pong Chu's writing style very easy to understand because the discussions are clear. That is the most essential thing in relaying knowledge to a beginner -- clarity. That's enough for me. I don't need to say more about it.

An FPGA Application

I think one of the more promising applications of FPGA is in real-time visualization. To be able to have a solid foundation on this, I need to study graphics first or say, Digital Image Processing. I am currently reading a documentation of the Master's thesis (March 2005) entitled An FPGA-based 3D Graphics System by Niklas Knutsson of Linköping Institute of Technology. His abstract goes like this.

This report documents the work done by the author to design and implement a 3D graphic system on an FPGA (Field Programmable Gate Array). After a preamble with a background presentation to the project, a very brief introduction in computer graphics techniques and computer graphics theory is given. Then, the hardware available to the project, along with an analysis of general requirements is examined. The following chapter contains the proposed graphics system design for FPGA implementation. A broad approach to separate the design and the eventual implementation was used. Two 3D pipelines are suggested - one fully capable high-end version and one which use minimal resources. The documentation of the effort to implement the minimal graphics system previously discussed then follows. The documentation outlines the work done without going too deep into detail, and is followed by the largest of the tests conducted. Finally, chapter seven concludes the project with the most important project conclusions and some suggestions for future work. 

I am after knowing the framework of such an application since there are already lots of books that discuss the physics of real-time graphics. I find quite few papers, much less books, that discusses the implementation of image processing on FPGA.

VHDL Part 51 : Debouncer

I find debouncing circuits very handy. Not only when I checked the test vector outputs of my design, but whenever I need to use a signal's event to trigger another signal. Debouncing solves the problem I encountered whenever I use the mechanical switches in the FPGA board particularly the push buttons. Mechanical switch bounces that when I push it once,  the output could be three times the supposed signal. Good thing, I tried the Xilinx ISE 9.2i in-depth guide before, I learned that ISE has a template for a debouncer. Templates are accessed by the icon below.

On the tree at the left of the Language Templates subwindow, expand VHDL, then Synthesis Constructs > Coding Examples > Misc > Debounce Circuits. I played with the code trying to put the statement for the output within the clock statement. I also inverted the signals used to solve the output. Debouncers have been very useful to me.

VHDL Part 50 : Accessing the Serial Port

I was such in a hurry that time when I had just finished porting the search algorithm I was working on to VHDL. It ran in the FPGA board but the results I see are on the LEDs. I cannot check the output with the LEDs since they are fast even if I had set the clock so slow for me to see the transitions I still cannot read with it. To be sure, I was adviced by my teammate to read the serial port using Matlab®. My inputs will be generated by a counter that with each count, it will give the necessary inputs to my main block. To do that I first need a UART transmitter and use the push-down button on the FPGA board as my clock. In using the push-down button as the clock, I need to add a debouncing circuit to control it because one push could give several clocks. This is what I did to access the serial port on the FPGA board I am using.

VHDL Part 49 : Re Mask Generator, Third Solution

Apparently, I am not the only one that has this problem. I had found a way to solve the mask generator problem by looking in forums such as the one posted in VelocityReviews titled VHDL - generic shift register where value 'n' keeps changing. Though our circuits are different, we both struggled with mapping the generics based on an input signal. The generics have to be compiled during runtime that's why I have errors as posted on the previous post (VHDL Part 48).  What Ralph Hildebrandt suggested in that post was to model a shift register (whatever component it is) wide enough for the worst case. He also noted that all the time, those flipflops is included. It was sound enough. That is what I followed. Whatever component I/O ports you put in the FPGA board has to be fixed for obvious reasons.

VHDL Part 48 : Mask Generator, Third Solution

I cannot use the second solution. The problem with it is that the inputs have to be fixed. The mask generator that we want to do has to be flexible where  the components' ports and signals depend on the length of the input. My teammate will give me an input for the valid length then I plan to convert it to integer and use it as a parameter with which I will map my subblock generics. The problem is this method produced errors all have to do with the following:

The actual value [signal_name] associated with a generic must be a globally static expression.

I have to look for another way.

'reconfiguration' in FPGA

My teammate and I are problematic (I know he is; he doesn't know I am) about the fact that VHDL does not support reconfiguration right now. Don't get me wrong. The technology is reconfigurable by the fact that it is an FPGA board. The abstract of our project says that what's good here is the 'reconfigurability' of the board we are using when you can't actually reconfigure the board during runtime. The bright side here, as I see it, is that this is another room for study. Maybe what will happen with us is that we will implement applications and tackle the problem as we encounter it. I haven't got much time to study it all. Seems like my next two years is already programmed. I'll burn the bridge when I get there.

VHDL Part 47: Mask Generator, Second Solution

I was thinking for another solution after those posts. My project leader suggested a design that I gladly worked on. It is done by cascading an encoder, a decoder, and a register. Then having several instances of this network depending on the pattern that I want to have. My outputs are obtained from the registers. The final output is obtained by having a selector decide which output index must be taken. I'm sorry I cannot post the code here. Intellectual property man..which I am very much against.

VHDL Part 46 : Mask Generator 5

And so I said:

jeppe,

1. I hadn't tried it yet in other languages.
2. I have been using paper and pen too for this thinking I might find some other way to manipulate the flow.
3. I am just considering 3 for n and 5 for r.

I did not pursue using arrays anymore for this mask gen. (Though I was glad to be able to try vhdl arrays). The fact that I will be inferring a large amount of combinatorial circuits made me decide to switch to other possible designs. This conversation took place March this year.

VHDL Part 45 : Mask Generator 4

To which he patiently replied:

My "fast" answer without getting into details.
1) Have you tried this algoritme in other languages like C or Java.
2) Have you draw the data structures at a paper checking the flow. 
3) A got a feeling your about to create a huge combinatorial network which in the end will take up to much space.
May be should you consider a "pipelined" design in which you works at parts of the arrays. This will however cost you time instead of logic.

Jeppe

VHDL Part 44 : Mask Generator 3

I tried his code and added some lines so that I could tap a row for the output. However, I could not view the RTL schematic so I posted a follow up question.

Hi jeppe

Thank you so much for helping me. 


I had added some lines of code so that I could access a row for the output.

for j in 0 to r-1 loop
for i in 0 to n-1 loop
if maskIn_P(i) = maskIn_R(j) then
memory(i)(j) <= '1'; --THIS IS LINE 68
else
memory(i)(j) <= '0'; end if; end loop; end loop; elsif readEn = '1' then maskOut <= memory(conv_integer(address)); else maskOut <= "ZZZZZ"; end if; end if; end process; 

Here's my port declaration:

address : in STD_LOGIC_VECTOR (r-1 downto 0);
patternIn : in STD_LOGIC_VECTOR (n-1 downto 0);
referenceIn : in STD_LOGIC_VECTOR (r-1 downto 0);
maskOut : out STD_LOGIC_VECTOR (n-1 downto 0));


I got no error in checking the syntax but got one when I tried to view the RTL schematic. 
line 68: Index value <8> is not in Range of array <0>>.

I'm not sure but I have a feeling that the error is caused by this line
maskOut <= memory(conv_integer(address));

Is it necessary for n and r to be equal? I had tried letting n be equal to 8 and r to 32
but it won't synthesize. When I tried using your values which is 10 for both, it did 
synthesize. So long as n and r are equal it synthesized. But I can't have have equal values for n and r 
since my reference vector must be much longer than my pattern vector.

Thanks again,
tahder

VHDL Part 43 : Mask Generator 2

Jeppe is kind enough to answer me. Here it goes.

Hi tahder

Not sure - but I guess the generate statement not allowed inside a process.

try this instead

---------------------------------------------------------------------------------- 
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity mskgen is 
   generic( n: natural := 10; 
             r: natural := 10); 
    port( clk,maskEn: std_logic); 
end mskgen; 

architecture bhv of mskGen is 
   subtype patternArray is std_logic_vector (n-1 downto 0); 
   type referenceArray is array (r-1 downto 0) of patternArray; 
   signal memory,maskIn_P,maskIn_R : referenceArray; 

begin 
    process (clk, maskEn) 
    begin 
        if clk = '1' and clk'event then 
            if maskEn = '1' then 
                for j in 0 to r-1 loop 
                    for i in 0 to n-1 loop 
                       if maskIn_P(i)=maskIn_R(j) then 
                           memory(i)(j) <= '1'; 
                        else 
                           memory(i)(j) <= '0; 
                        end if; 
                    end loop; 
                end loop; 
            end if; 
        end if; 
    end process; 
end bhv;  

Regards
Jeppe

VHDLPart 42 : Mask Generator 1

Let me share the conversation that I had with jeppe from the vhdl forum in VelocityReviews. This is the question I posted (taht was March 2008).

Hello everyone,
I am new to vhdl and I want to implement a synthesizable mask generator. 
I thought about implementing it with a 2D array (like a ROM) that is usually seen in vhdl books.
My problem is that I'm stuck with generating the contents inside the array since an index will output a '1' only if an n-bit element is equal to another n-bit element. I don't want to have a build up of equality comparators. Is it possible to have only one comparator for the whole system? or a single row of comparators that will work for all the rows in the memory? I tried doing this:

architecture bhv of maskGen is

subtype patternArray is std_logic_vector (n-1 downto 0);
type referenceArray is array (r-1 downto 0) of patternArray;
signal memory : referenceArray;

-- this is for the magnitude comparator
component magComp
port (A, B : in std_logic_vector (n-1 downto 0);
EQ : out std_logic);
end component;

-- The behavioral architecture for magComp is only:
-- EQ <= '1' when A=B else '0'; begin process (rst, clk, maskEn) begin if clk = '1' and clk'event then if maskEn = '1' then for j in 0 to r-1 loop for i in 0 to n-1 generate -- this is line 69 magComp port map (A=>maskIn_P(i), B=>maskIn_R(j), EQ => memory(i)(j));
end generate;
end loop;
end if;
end if;

end process;
end bhv;


However, this gave me an error:
Line 69. parse error, unexpected GENERATE, expecting LOOP.

Can anyone explain why the code generated such an error? 

I really do not want to implement the code above since it might result to horrendous amount of logic.
What do I do now? 

Thanks,
tahder

VHDL Part 41 : Arrays

I happen to take interest in vhdl arrays when I was trying to come up with a code for mask generator. A mask generator is like a multplication table where you have values along x and along y and to get a '1', certain values for x and y must be satisfied. I was trying to come up with a design that won't build a tremendous amount of logic so I tried to check out arrays.

Arrays in VHDL can be 1D, 2D or 1Dx1D.

Here is a scalar : 0

Here is a 1D : 

11001

Here is a 1Dx1D :

11001

10100

00101

11100

Here is a 2D :

1 1 0 0 1

1 0 1 0 0

0 0 1 0 1

1 1 1 0 0

I just have a problem with these. According to the book Circuit Design with VHDL, they are generally not synthesizable. 

Reference:

(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.

VHDL Part 40 : Declaring Components in Packages

If I use a code as a component, I can then use it in another circuit which allows me to create designs in hierarchy. I find this good since it enables code reusability. However, I find it tiring to declare codes/components again and again everytime I revise my topblock. I sometimes place these components in a library so that I can do away with explicitly writing such codes.

For instance I need to instantiate a shift register, 4-bit  register, a decoder and an encoder. So first I have to create individual codes for each of these 4 circuits. You may see my previous posts for their sample codes. 

4-bit register -- VHDL Part 5

shift register -- VHDL Part 10

encoder -- VHDL Part 29

decoder -- VHDL Part 26

What I will write here now is the way I package my components and then proceed to the topblock. I will not make use of generics here.

----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

package component1 is

-- *********************

-- here's the 4-bit register

-- *********************

component ckt_reg is

Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
loadEn : in STD_LOGIC;
reg _in : in STD_LOGIC_VECTOR (regCount-1 downto 0);
reg _out : out STD_LOGIC_VECTOR (regCount-1 downto 0));
end component;

-- **************************

-- here's the 4-bit shift register

-- **************************

component shiftReg is

Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
shiftEn : in STD_LOGIC;
sh_in : in STD_LOGIC;
shReg _in : in STD_LOGIC_VECTOR (3 downto 0);
shReg _out : out STD_LOGIC_VECTOR (3 downto 0));
end component;

-- *****************

-- here's the encoder

-- *****************

component encode1 is

Port ( enc_in : in std_logic_vector (3 downto 0);
enc_out : out std_logic_vector(1 downto 0));
end component;

-- *****************

-- here's the decoder

-- *****************

component decode1 is

Port ( clk : in std_logic;
rst : in std_logic;
dec_in : in std_logic_vector (1 downto 0);
dec_out : out std_logic_vector(7 downto 0));
end component;

end component1;

----------------------------------------------------------------------------------------------------------

-- *******************************

-- here's my topblock

-- *******************************

----------------------------------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

use work.component1.ALL;

entity top1 is
port(
clk : in std_logic;
rst : in std_logic;

en : in std_logic;

top_sh : in std_logic; -- for shift register
top_in : in std_logic_vector (1 downto 0);
top_out : out std_logic_vector(decWidth-1 downto 0)
);

end top1;

architecture struct of top1 is

signal tmpReg2Sh, tmpSh2Enc :  std_logic_vector (3 downto 0);

signal tmpEnc2Dec :  std_logic_vector (1 downto 0); 

begin

-- I will use positional mapping here

COMP1 : ckt_reg port map (clk, rst, en, top_in, tmpReg2Sh);

COMP2 : shiftReg port map (clk, rst, en, top_sh, tmpReg2Sh, tmpSh2Enc);

COMP3 : encode1 port map (tmpSh2Enc, tmpEnc2Dec);

COMP4 : decode1 port map (clk, rst, tmpEnc2Dec, top_out);

end struct;

----------------------------------------------------------------------------------------------------------

Here's the catch: I was not able to simulate this due to my tight schedule. But if there are any errors, I expect them to be minor.

References:

(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.
(2) Xilinx Toolbox

CSIE 2009 Call for Papers

Ooops..so sorry for posting this conference invite so late..anyway, here it is.

----------------------------------------------------------------------------

2009 World Congress on Computer Science and Information Engineering
(CSIE 2009)

March 31 - April 2, 2009
Los Angeles/Anaheim, USA

http://world-research-institutes.org/conferences/CSIE/2009

CALL FOR PAPERS & EXPO

The Los Angeles/Anaheim area is known for its many renowned
attractions, such as Disneyland, Universal Studios and the
Hollywood Walk of Fame. Very few cities in the world offer
as much entertainment, excitement and diversity as Los
Angeles/Anaheim does.

CSIE 2009 intends to be a global forum for researchers and
engineers to present and discuss recent advances and new
techniques in computer science and information engineering.
CSIE 2009 consists of the following Technical Symposiums:

 * Communications & Mobile Computing Symposium
 * Computer Applications Symposium
 * Computer Design & VLSI Symposium
 * Data Mining & Data Engineering Symposium
 * Intelligent Systems Symposium
 * Multimedia & Signal Processing Symposium
 * Software Engineering Symposium

CSIE 2009 conference proceedings will be published by the IEEE
Computer Society and all papers in the proceedings will be
included in EI Compendex, ISTP, and IEEE Xplore.

In addition to research papers, CSIE 2009 also seeks exhibitions
of modern products and equipment for computer science and
information engineering.

Important Dates:

Paper/Abstract Submission Deadline: September 30, 2008
Review Notification: November 15, 2008
Final Papers and Author Registration Deadline: December 7, 2008

Organizing Committee:

General Chair:
Adrian Martin, World Research Institutes, USA

Program Chair:
Mark Burgin, University of California at Los Angeles, USA

Symposium Chairs:
Chan H. Ham, University of Central Florida, USA
Simone Ludwig, University of Saskatchewan, Canada
Weilian Su, Naval Postgraduate School, USA
Sumanth Yenduri, University of Southern Mississippi, USA

Publicity Chair:
Nitin Upadhyay, Birla Institute of Technology and Science
(BITS), India


(Please forward to those who may be interested.)

VHDL Part 39 : Packages in VHDL

I am now studying how to create packages in VHDL. Packages contain common design modules that I can use in VHDL source codes. By 'common design modules', I am referring to components, functions and procedures. Components I know so I will start on this. Structural programming has done me good in my  past VHDL designs since it gives me a much cleaner look and modularity. But it can be very exhausting for me especially whenever I am instantiating several components again and again. This often happens to me since I do not delete my code revisions. I can do copy-paste in component declarations; however, I want to try package and see which eases my tasks better. See you in my next post for a sample code on this trial of mine!

5-meter distance

I know this is not something to wonder about in this generation. But because I love science and [Einstein is here], I decided to post this.


When you have a closer look at this picture, you see Albert Einstein.
When you look at it from a 5-meter distance, you see Marilyn Monroe.

Willpower

I had received this email from my sister. I think it would be worthwhile to share this with you..

I indeed smiled after seeing the pictures..

Here it goes..

You thought the dog is imitating the man.

Entertains college(?) kids.

Have a closer look

Despite being an animal he gets respect and welcome..

loving pats on the back..

There are a lot of open things we can do..
we just have to believe and will that we can..

VHDL Part 38 : Finite State Machine Sample Design Simulation Results

I tried simulating the fsm1.vhd code [I had posted before this one]. Let me show you my testbench.

Here's my simulation results.

And yes. It produced my desired outputs :).

VHDL Part 37 : Finite State Machine Sample Design Code

I had already illustrated the states I want my signals to go through. I have learned that to be able to design a state machine, I need one combinational and one sequential processes. So now I need to code it.

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fsm1 is
port(
clk : in std_logic;
rst : in std_logic;
cond_1 : in std_logic;
cond_2 : in std_logic;
block1_en : out std_logic;
block2_en : out std_logic;
block3_en : out std_logic;
block4_en : out std_logic);
end fsm1;

architecture Behavioral of fsm1 is

-- let me declare my states by enumeration; the present state and next states as signals, the
-- data type of which is my list of states (fsmState)
type fsmState is (idleState, state1, state2, state3, state4);
signal presentState, nextState : fsmState;

begin

-- here's my sequential process
seq_process : process (clk,rst)
begin

if rst = '1' then 

-- idleState is the default state
presentState <= idleState; 

elsif clk'event and clk = '1' then 

presentState <= nextState; 

end if;
end process seq_process;

-- here's my combinational process
comb_process : process (presentState, cond_1, cond_2)
begin

case presentState is

when idleState =>

-- all my blocks are disabled
block1_en <= '0';
block2_en <= '0';
block3_en <= '0';
block4_en <= '0

-- at the next clock (as seen on the sequential process), my next state will be state 1
nextState <= state1; 

when state1 =>

-- enable only block1
block1_en <= '1';
block2_en <= '0';
block3_en <= '0';
block4_en <= '0'; 

-- conditions changed?
if ((cond_1 = '1') and (cond_2 = '0')) then

nextState <= state2;

elsif ((cond_1 = '0') and (cond_2 = '1')) then

nextState <= state3; 

else

nextState <= idleState; 

end if;

when state2 =>

-- enable only block2
block1_en <= '0'; 
block2_en <= '1'; 
block3_en <= '0'; 
block4_en <= '0'; 

-- conditions changed?
if ((cond_1 = '1') and (cond_2 = '0')) then

nextState <= state4; 

else

nextState <= state2; 

end if;

when state3 =>

-- enable only block3
block1_en <= '0'; 
block2_en <= '0'; 
block3_en <= '1'; 
block4_en <= '0'; 

-- conditions changed?
if ((cond_1 = '0') and (cond_2 = '1')) then

nextState <= state4; 

else

nextState <= state3; 

end if;

when state4 =>

-- enable only block4
block1_en <= '0'; 
block2_en <= '0';
block3_en <= '0'; 
block4_en <= '1';

-- conditions changed?
if ((cond_1 = '1') and (cond_2 = '1')) then

nextState <= state1;

else

nextState <= state4; 

end if;
end case;
end process comb_process;
end Behavioral;
----------------------------------------------------------------------------------
I did not have any warnings when I synthesized it. When I tried closing the cases in my case statement with

------------------------------
when others =>

nextState <= presentState;
------------------------------

I have the following warnings

------------------------------
WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:1294 - Latch is equivalent to a wire in block .
WARNING:Xst:1294 - Latch is equivalent to a wire in block .
WARNING:Xst:1294 - Latch is equivalent to a wire in block .
WARNING:Xst:1294 - Latch is equivalent to a wire in block .
------------------------------

Ok. I had already completed my case statement with when others. Why is it that I still have WARNING:Xst:737? After I read the warnings carefully, I noticed that ISE has given my outputs latch equivalents which I do not want because it seems to me that my outputs are not clocked. I tried adding the outputs to my when others like so

------------------------------
when others =>

block1_en <= '0'; block2_en <= '0'; block3_en <= '0'; block4_en <= '0'; nextState <= presentState;
------------------------------

The warnings then disappeared.

Yehey ;)

Reference:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.

VHDL Part 36 : Finite State Machine Sample Design Illustration

So I want to design and simulate a state machine using VHDL. First, since I am a starter, I must have an illustration of want I want my circuit to go through. I have made a very simple flow as illustrated below.

And here's what I want to happen at each state.

I then need I/O ports of course. For my inputs, I'll have clk (master clock), rst (master reset) and cond_1 and cond_2 as conditions. My outputs will be the enables of my 4 blocks.

VHDL Part 35 : WARNING:Xst:1710 and WARNING:Xst:1895

I had encountered this two warnings while designing a counter.

WARNING:Xst:1710 - FF/Latch count_0 (without init value) has a
constant value of 0 in block block_name. This FF/Latch will be
trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch count_1
(without init value) has a constant value of 0 in block block_name.
This FF/Latch will be trimmed during the optimization process. 

I think the following is due to the fact that I'm incrementing by 4 which is "100" in binary form. The last two bits indeed will always be zero. And so to optimize this block, the device that will store them will be trimmed. I tried incrementing by 1. As expected, the warnings disappeared so I ignored them.

VHDL Part 34 : ERROR:HDLParsers:3566

I encountered this error while making my codes for this blog (that time I was still using version 9.1).

ERROR:HDLParsers:3566 - xst/work/hdpdeps.ref line 2 Invalid date/time ("Blog/dFF/dFF.vhd") found.

I again searched for it and this site helped.

What happened to me was I saved the project in c>xilinx>for Blog (because I was testing if the error in the previous post will appear again) then i copied and pasted the dFF file from other folder in the same path.

VHDL Part 33 : ERROR:HDLParsers:3562

Before I proceed with FSM, let me share this.

I was using Xilinx ISE 9.1 before and had encountered this error

ERROR:HDLParsers:3562 - project_name line_# Expecting 'vhdl' or 'verilog' keyword, found 'work'.

I was already getting bugged with this error because I don't understand what it wants to convey. Until I landed on this site.

There are a couple or more ways the kind people there suggested on how to get rid of that error. I tried the easiest one which is to store the project in a directory path that has no spaces. I was saving my projects in My Documents folder. So I transferred all my projects under Xilinx ISE folder and there. The error disappeared. I find this bug is kind of funny too. I then switched to version 10.1.

VHDl Part 32 : Finite State Machines (FSM)

I'm back..I have been very busy these past few days coding a block that would interface a dual-port block, a software control and sdram controller. So I got lost in circulation :).

The first time I encountered FSM was when it was taught in the class. It hadn't appealed to me much since it was only a one day discussion and more on theories. We didn't actually code it. When a training in the basics of Xilinx ISE was held in our office this year, it caught my interest. I just realized how useful state machines are and so I decided to blog about it. The only book that got me going in using FSM is the one by Pedroni, V., Circuit Design with VHDL. Here's some points I got from that book.

In constructing a single FSM you need two process, one combinational and one sequential.

That's it! heheh.. Well, there are some primers the author gave like the Moore-Mealy machines. It's much better discussed by him so you just check out his book.

To better understand FSM I need to study the design samples in the book and then try to come up with my own. And that's what I will blog next!

Still have a lot to learn

Sometimes I ask myself why I am still not posting anything about DSP. DSP has been my most loved subject in school. I have this strong feeling that there's something in it. I don't know what that something is but I want to find it out. However, I didn't learn anything from the class and almost flunked it. But the feeling is still there. There are a lot of books that explains about it but my problem with them is that there are too many dumb equations because I can't understand what they are telling me. When I come across FPGA, I tried to search about its applications. I was so thrilled to see that dsp is one of them. I thought that maybe fpga can help me see beyond those equations and understand the concept behind them. If I can make it help me visualize what the equation parameters do to a certain phenomena, then I will better understand the power of dsp and manipulate the math. The drive is so much I cannot ignore it. Until I watched the movie Babe and heard the narrator say, "But farmer Hogget knew that little ideas that tickled and nagged and refuse to go away should never be ignored for in them lie the seeds of destiny."


Yeaaaaaaah..I still have a lot to learn and the things I post here may seem little steps. But they will take me there. DSP is hard. It becomes much harder when you code it in hardware. I think I must master fpga first and insert some math, and more math and complicated math and more complicated math..until I reach dsp. Takes long time, eh? But still I will take these teeny-weeny steps. At least they keep me moving forward...

VHDL Part 31 : VHDL Part 30's warnings

I am now using ISE version 10.1..I had encountered some warnings in the previous version that were just bugs but already cured in 10.1.

Please see VHDL Part 30 for the code.

The synthesis of MUX code I had posted previously completed successfully. However, it gave me the following warnings on the Transcript subwindow (subwindow at the bottom):
(1) WARNING:Xst:819 - "C:/Xilinx/10.1/tahder/scratch/mux1/mux1.vhd" line 44: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
(2) WARNING:Xst:737 - Found 2-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

Some people ignore warnings since the design still runs during simulation. I don't as they warn :) me of some problems that might occur during my synthesis. By 'synthesis' I mean when you implement this on the FPGA board. Some warnings are okay, while some can be removed as in the case with this code. To view full info on the warning, see the Design Summary (if not already open, double click View Design Summary on the Processes Subwindow, the one with the green upper case sigma icon).

Here's how I removed those warnings.

(1) Guided by the Design summary, the inputs mux_in1, mux_in2, mx_in3 and mux_in4 must be included in the process sensitivity list. The process line must be

mux_process : process (mux_sel, mux_in1, mux_in2, mux_in3, mux_in4)

(2) This error is explained by Xilinx as stated above. Remember that latches are not clocked and this may lead to synthesis problems. The two-bit latch that were generated are due to the following lines were mux_out2 are not specified.

when "10" => mux_out1 <= mux_in3;
when "11" => mux_out1 <= mux_in4;

If you still decide to go on with simulation in spite of this warning you will have the following result:
Notice mux_out2 values enclosed by the two markers, between times (200ns and 300ns) and (800ns and 900ns). The selector mux_sel has the same value for both time ranges ("11") but they have different mux_out2. That is also what happened with the value of mux_out2 between times (100ns and 200ns) abd (1100ns and 1200 ns) when mux_sel is "10". The reason for this is that the two values of mux_sel ("10" and "11") do not have any mux_out2 specified for them. And so they will just take the value of whatever specified mux_out2 that precedes them. Notice that the mux_out2 for mux_sel "00" and "01" are specified. Whenever these two ("00" and "01") precedes the other ("10" and "11"), the latter two will just take the mux_out2 of the former two.

The way I get around this is that I assign values for all outputs. However, if I don't want to be specific with some of them and I just don't care what their outputs are, use 'X' which is for assigning all unknown or don't care values. And so the case statement must be

when "00" => mux_out1 <= mux_in1; mux_out2 <= "0011";
when "01" => mux_out1 <= mux_in2; mux_out2 <= "0010";
when "10" => mux_out1 <= mux_in3; mux_out2 <= (others=>'X');
when "11" => mux_out1 <= mux_in4; mux_out2 <= (others=>'X');
when others =>

And my simulation result is


which is what I expected.

Going back to the case statement, I may assign "XXXX" to mux_out2 which is a bit vector. However, if the length of my vector is something like 256, using (others=> ) will be very handy.

Also, you may notice the last two lines

when "11" => mux_out1 <= mux_in4; mux_out2 <= (others=>'X');
when others =>

You may say that since there are only 4 possible inputs, why don't I just put these two in one line.

when others => mux_out1 <= mux_in4; mux_out2 <= (others=>'X');

Well, I did it to be sure during synthesis. I may also do something like

when "11" => mux_out1 <= mux_in4; mux_out2 <= (others=>'X');
when others => mux_out1 <= (others=>'0'); mux_out2 <= (others=>'X');

which is also okay (for me).

;)

References:
(1) Pedroni, V., Circuit Design with VHDL, The MIT Press, 2004.
(2) Xilinx MUX Toolbox